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TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival
by Daniel Nenni on 11-07-2025 at 6:00 am
Categories: AI, Automotive, Foundries, TSMC

TSMC Kumamoto Fab 2

In the lush landscapes of Kumamoto Prefecture, on Japan’s Kyushu Island, TSMC is etching a new chapter in global chip production. The TSMC Kumamoto facility, operationalized through its wholly-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM), represents the Taiwanese giant’s bold foray into Japan, the first dedicated wafer fab outside Taiwan, the U.S., and Europe.

Announced in 2021, this project embodies a strategic pivot toward diversified, resilient manufacturing. With an initial investment exceeding $8.6 billion, Kumamoto underscores TSMC’s commitment to serving key Asian clients while bolstering Japan’s domestic semiconductor ecosystem.

The journey began with groundbreaking in 2022, transforming a sprawling industrial site in Kikuyo Town into a state-of-the-art cleanroom. Construction progressed swiftly, with Taiwanese engineers relocating en masse to oversee integration. By late 2024, JASM’s first fab commenced mass production, focusing on mature yet vital process nodes: 22/28nm and 12/16nm. These nodes are ideal for automotive semiconductors, image sensors, and microcontrollers, sectors where Japanese powerhouses like Sony and Denso dominate.

The facility’s monthly capacity targets 55,000 wafers, powered entirely by renewable energy sources, aligning with Japan’s green manufacturing mandates. As of April 2025, JASM’s workforce has swelled to around 2,400, including 527 new local hires, fostering a blend of Taiwanese expertise and Japanese precision. This infusion has not only created jobs but also sparked a skills renaissance in Kyushu, a region long synonymous with electronics but starved of cutting-edge fabs. This fab was dubbed the “Knight Castle” by locals since construction was done 24 hours a day.

Kumamoto’s strategic imperative is twofold: Geopolitically, it mitigates risks from Taiwan’s exposure to cross-strait tensions, diversifying TSMC’s footprint amid U.S.-China frictions. Economically, it taps into Japan’s resurgence under the “Semiconductor Revival Plan,” backed by subsidies from the Ministry of Economy, Trade and Industry.

This funding is part of a national initiative which aims to reclaim 10% of global chip production by 2030. For TSMC, Kumamoto secures proximity to loyal customers: Sony’s image sensors for smartphones and cameras, Denso’s automotive chips for electric vehicles, and emerging AI peripherals. In an era where automotive semis face slumps, exacerbated by delayed EV adoption, the fab’s specialization offers stability. Industry watchers project profitability by late 2025, with yields already performing robustly.

Yet, expansion hasn’t been seamless. The second fab, earmarked for advanced 6/7nm processes on a 321,000-square-meter plot adjacent to the first, has encountered headwinds. Initially slated for Q1 2025 groundbreaking, construction was deferred to mid-year due to severe traffic congestion from the initial site’s operations (commutes ballooning from 15 minutes to an hour) irking residents. TSMC Chairman C.C. Wei cited these local pains during the June 2025 shareholders’ meeting, emphasizing dialogues with Japanese authorities for infrastructure upgrades. Further delays in 2025 stemmed from softer automotive demand and a pivot toward U.S. investments, pushing mass production to late 2027. TSMC builds fabs closely tied to customer demand so this a good example of intelligent semiconductor business decisions.

Despite these challenges, TSMC reaffirmed its commitment in August 2025 with board member Paul Liu quashing rumors of diminished Japanese focus. The second fab promises elevated capabilities, including 40nm variants for industrial applications, potentially doubling output and attracting more clients.

Beyond wafers, Kumamoto catalyzes regional transformation. Kyushu’s IC production value hit ¥1 trillion in 2024 for the first time in 16 years, fueled by TSMC’s ripple effects. Local suppliers, from equipment makers to materials firms, now furnish 60% of needs, nurturing a self-sustaining cluster. Governor Takashi Kimura has championed community buy-in, securing promises for green spaces and training programs amid wastewater monitoring starting January 2025.

Bottom live: Kumamoto could spawn a third fab post-2030, embedding TSMC deeper in the “semiconductor triangle” of Taiwan, Japan, and the U.S. As AI and EVs propel chip demand, this outpost fortifies supply chains, blending Eastern innovation with Western resilience. In Kumamoto, silicon flows not just as commerce, but as a bridge across borders proving that in the chip wars, collaboration outpaces isolation. For TSMC, it’s a testament to enduring partnerships, for Japan it is a revival etched in silicon, absolutely.

Also Read:

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

Exploring TSMC’s OIP Ecosystem Benefits

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging

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Memory Matters: The State of Embedded NVM (eNVM) 2025

Memory Matters: The State of Embedded NVM (eNVM) 2025
by Daniel Nenni on 11-06-2025 at 6:00 am
Categories: GlobalFoundries, IP, Samsung Foundry, TSMC
1 Comment

NVM Survey 25 Square Banner for SemiWiki 400x400 px

Make a difference and take this short survey. It asks about your experience with embedded non-volatile memory technologies. The survey is anonymous, and the results will be shared in aggregate to help the industry better understand trends: 2025 Embedded Non-Volatile Memory Survey.

We are now in the AI era where data is the lifeblood of innovation, and embedded NVM stands as a cornerstone technology, retaining information without using power and enabling everything from MCUs and IoT SoCs to automotive controllers and secure elements.

As of November 2025, embedded NVM is moving fast. Edge data is surging, AI features are landing on MCUs and SoCs, and power budgets are tighter than ever. Memory is central to the devices we build. This survey looks at where eNVM stands today in terms of markets, technology, and adoption, and where it’s heading next.

Market Overview and Growth

Embedded emerging NVM, including MRAM, RRAM/ReRAM, and PCM, is entering a broader adoption phase across MCUs, connectivity, and edge-AI devices, with momentum building in automotive and industrial markets. Research firm Yole Group indicate the embedded emerging segment should exceed $3B by 2030, reflecting wider availability in mainstream process nodes and stronger pull where eFlash is no longer a good fit at ≤28 nm.

Technological Advancements

Embedded flash remains foundational, but scaling limits at advanced nodes have pushed MRAM, ReRAM, and embedded PCM to the foreground. Foundries and IDMs are extending embedded options beyond 28/22 nm planar CMOS toward 10–12 nm-class platforms, including FinFET. Yole highlights aggressive foundry roadmaps: TSMC has established high-volume MRAM/ReRAM and is preparing 12nm FinFET ReRAM/MRAM for 2025 and beyond. Samsung, GlobalFoundries, UMC, and SMIC are accelerating embedded MRAM/ReRAM/PCM across general-purpose MCUs and high-performance automotive designs. STMicroelectronics stands out as the IDM fully committed to embedded PCM, ramping xMemory solutions for industrial and automotive MCUs, with 18nm FD-SOI extending reach after 2025.

In parallel, BCD and HV-CMOS flows are incorporating embedded NVM as practical replacements for EEPROM/OTP in analog, power management, and mixed-signal designs. On the IP side, suppliers are qualifying embedded NVM technologies for these platforms, giving designers more options where cost, endurance, and retention outweigh legacy choices. Beyond code and data storage, in-/near-memory compute concepts using eNVM are gaining interest for low-power edge AI inference.

Drivers, Challenges, and Use Cases

Automotive remains the center of gravity for embedded emerging NVM, and 2025 brings a noticeable uptick in secure ICs and industrial MCUs as more products reach production. In practice, ReRAM, MRAM, and PCM each have a role: ReRAM is gaining traction in several high-volume categories; MRAM and PCM are attractive where speed and endurance dominate. The mix varies by node, application, and vendor roadmap.

The challenges are familiar: integrating eNVM at advanced logic nodes, trading off endurance and retention, qualifying to automotive-grade reliability, and achieving cost-effective density as embedded code and AI parameters grow. The trend line is positive, with PDK/IP availability growing and capacity ramping, so these issues are being addressed rather than deferred.

Outlook

By 2030, embedded NVM will underpin more on-chip AI features and practical in-/near-memory compute blocks, with broader use in neuromorphic-inspired accelerators at the edge. Yole’s projections indicate that the embedded emerging segment is now the primary engine of growth, led by ReRAM in high-volume MCUs and analog ICs, while MRAM and embedded PCM consolidate in performance-critical niches. As edge data grows, eNVM’s role expands from “just storage” to part of the computing fabric, redefining efficiency and making embedded memory more central than ever to device intelligence.

Bottom line: In 2025, embedded NVM isn’t just memory, it’s the enabler of intelligent, persistent systems on chip. With accelerating adoption across MCUs and edge SoCs, and clear roadmaps from leading foundries and IDMs, the trajectory is set: embedded memory matters more than ever. Let us know your opinion by taking the short survey.

Take the 2025 Embedded Non-Volatile Memory Survey Here.

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AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design
by Daniel Nenni on 10-28-2025 at 10:00 am
Categories: EDA, Events, Foundries, Siemens EDA, TSMC

AI Driven DRC Productivity Optimization Siemens AMD TSMC

The semiconductor industry is undergoing a transformative shift with the integration of AI into DRC workflows, as showcased in the Siemens EDA presentation at the 2025 TSMC OIP. Titled “AI-Driven DRC Productivity Optimization,” this initiative, led by Siemens EDA’s David Abercrombie alongside AMD’s Stafford Yu and GuoQin Low, highlights a collaborative effort to enhance productivity and efficiency in chip design. The presentation outlines a comprehensive AI system that revolutionizes the entire EDA workflow, from knowledge sharing to automated fixing and debugging.

At the core of this innovation is the Siemens EDA AI System, which leverages a GenAI interface, knowledge base, and data lake to integrate AI tools across the portfolio. This system, deployable on customer hardware or cloud environments, supports a unified installation process and offers flexibility to incorporate customer data and models. Tools like the AI Docs Assistant and Calibre RVE Check Assist boost user understanding by providing instant answers and leveraging TSMC design rule data, respectively. The AI Docs Assistant, accessible via browser or integrated GUIs, uses retrieval-augmented generation to deliver relevant citations, while Calibre RVE Check Assist enhances debugging with specialized images and descriptions from TSMC.

Collaboration is a key pillar, with features like Calibre RVE Check Assist User Notes enabling in-house knowledge sharing. Designers can capture fixing suggestions and images, creating a shared knowledge base that enhances DRC-fixing flows across organizations. Meanwhile, Calibre DesignEnhancer automates the resolution of DRC violations on post-routed designs, using analysis-based modifications to insert sign-off DRC-clean interconnects and vias. This tool’s ability to handle complex rules and dependencies makes it a standalone DRC fixing solution.

Calibre Vision AI addresses the unique challenges of full-chip integration by offering AI-guided DRC analysis. It provides lightning-fast navigation through billions of errors, intelligent debug clustering, and cross-user collaboration tools like bookmarks and HTML reports. AMD’s testimonial underscores a 2X productivity boost in systematic error debugging, with Vision AI reducing OASIS database sizes and load times significantly. Signals analysis, such as identifying fill overlaps with clock cells or CM0 issues in breaker cells, accelerates root-cause identification.

This AI-driven approach, bolstered by AMD and TSMC collaborations, optimizes DRC sign-off productivity by boosting workflows, understanding, fixing, debugging, and collaboration. As the industry moves toward more complex designs, Siemens EDA’s AI system sets a new standard, promising faster cycle times and enhanced design robustness, paving the way for future innovations in semiconductor technology.

For more information contact Siemens EDA

Great presentation, absolutely.

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Exploring TSMC’s OIP Ecosystem Benefits

Exploring TSMC’s OIP Ecosystem Benefits
by Daniel Nenni on 10-10-2025 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, Events, Foundries, IP, TSMC

TSMC Booth

Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC with EDA providers, IP developers, cloud partners, design centers, and value chain players. This network, now spanning over 100 partners, has invested trillions of dollars cumulatively to align around TSMC’s technology roadmap, enabling faster innovation and specialization. As of 2025, OIP continues to evolve with recent expansions like the 3DFabric Alliance accelerating 3D IC advancements for AI and HPC.

The ecosystem’s core strength lies in its comprehensive alliances: EDA Alliance for certified tools, IP Alliance for silicon-verified blocks, Cloud Alliance for scalable design environments, Design Center Alliance (DCA) for expert services, Value Chain Alliance (VCA) for backend support, and specialized groups like 3DFabric for advanced packaging. These components lower barriers, ensuring “first-time silicon success” and driving shared value. Below, we break down the primary benefits for customers (chip designers), partners, and the broader industry.

1. Accelerated Design and Time-to-Market

OIP drastically shortens the path from concept to production, addressing the semiconductor industry’s relentless pace. By integrating TSMC’s process technologies with partner tools and IP, it reduces design cycle times by providing pre-validated interfaces and flows.

For instance:
  • Cloud-Based Design: Through the Cloud Alliance (partners like AWS, Google Cloud, and Microsoft Azure), customers overcome in-house compute limits, enabling “design-in-the-cloud” for scalability and agility. This has cut time-to-market for complex chips by weeks to months.
  • AI-Assisted Flows: At the 2024-2025 OIP Forums, ecosystem demos showcased AI-optimized 2D/3D IC designs, boosting productivity for AI and 5G applications.
  • 3D Innovation: The 3DFabric Alliance, launched in 2022, speeds silicon stacking and chiplet integration, as seen in AMD’s TSMC-SoIC-based CPUs, which achieved energy-efficient HPC breakthroughs.

Statistics highlight the impact: OIP has enabled over 1,800 chip tape-outs, with partners like Silicon Creations contributing to 1,000+ advanced-node designs. Testimonials from Synopsys emphasize how OIP’s multi-die tools deliver “powerful and efficient processing” for hyperscale computing.

2. Cost Reduction and Efficiency Gains

OIP minimizes financial risks by democratizing access to premium resources, allowing smaller firms to compete with giants.

  • Lower Barriers: Silicon-verified IP catalogs (the industry’s largest) and EDA certifications reduce R&D duplication, cutting development costs by up to 30-50% through reusable blocks like PLLs and SerDes.
  • Shared Investments: Ecosystem collaborations, backed by billions in annual spending, spread costs across partners. For example, Siemens EDA Calibre 3DThermal integration with TSMC processes provides thermal analysis without custom tooling.
  • Design Services: DCA and VCA offer outsourced expertise for testing and packaging, ideal for resource-constrained teams.

This efficiency has been pivotal for mobile and IoT innovations, where rapid prototyping via OIP’s Virtual Design Environment (launched 2018) avoids expensive iterations.

3. Enhanced Collaboration and Ecosystem Synergy

OIP’s “partner management portal” via TSMC-Online fosters seamless communication, turning competition into co-creation.

  • Supply Chain Alignment: Standardized interfaces (e.g., 3Dblox for chiplet packaging) ensure interoperability, as noted by Siemens EDA: “OIP has been pivotal to advancing certified flows.”
  • Global Forums: Annual events like the 2025 North America OIP Forum in Santa Clara unite 1,000+ attendees for multi-track sessions on AI, photonics, and RF, sparking real-time problem-solving.
  • Award-Winning Partnerships: 2025 honorees like Teradyne (for 3DFabric testing) and Silicon Creations (ninth straight Mixed-Signal IP award) exemplify how OIP drives mutual growth, with TSMC’s Aveek Sarkar praising their role in “energy-efficient AI chip innovation.”
4. Industry-Wide Innovation and Scalability

Beyond individual gains, OIP propels the sector forward by supporting emerging tech like 2nm nodes, UCIe standards, and silicon photonics. It has nurtured innovations in automotive, 5G, and edge AI, with partners like imec contributing R&D for low-volume prototyping. The result? A resilient ecosystem that shortens “time-to-revenue” while promoting sustainability through efficient designs.

Bottom line: TSMC’s OIP transforms semiconductor development from siloed efforts to a vibrant, collaborative powerhouse. As AI demands surge, its benefits of speed, savings, synergy, and scalability position it as indispensable, empowering innovators to outpace Moore’s Law. For deeper dives, explore TSMC’s OIP page and the most recent forum recap: TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging.

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Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

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Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®
by Daniel Nenni on 10-08-2025 at 8:00 am
Categories: Foundries, TSMC

ETC 2025 TSMC

In a landmark presentation at the 2025 IEEE Electronic Components and Technology Conference (ECTC), TSMC unveiled a groundbreaking advancement in thermal management: Direct-to-Silicon Liquid Cooling integrated directly onto its CoWoS® platform. This innovation, detailed in the paper “Direct-to-Silicon Liquid Cooling Integrated on CoWoS® Platform,” addresses the escalating thermal challenges posed by HPC and AI applications, where power densities are surging beyond traditional cooling limits. As AI accelerators and data center chips push thermal design power toward kilowatt levels, TSMC’s solution promises to shatter the “thermal wall,” enabling denser, faster, and more efficient semiconductor designs.

The “thermal wall” refers to the fundamental barrier where heat generation outpaces dissipation capabilities, throttling performance and reliability in advanced nodes. With the rise of 2.5D/3D packaging technologies, chips now integrate multiple dies, high-bandwidth memory (HBM) stacks, and interposers on a single package, amplifying power densities to over 4.8 W/mm². Air cooling, once sufficient for consumer-grade processors, falls short for HPC workloads. Even advanced air-cooled heatsinks struggle with TDPs exceeding 1 kW, leading to hotspots that degrade silicon integrity and limit clock speeds. Liquid cooling has emerged as a necessity, but conventional methods—relying on bulky external loops or thermal interface materials (TIMs)—introduce inefficiencies, adding thermal resistance and manufacturing complexity.

TSMC’s Direct-to-Silicon Liquid Cooling redefines this paradigm by embedding microfluidic channels directly into the silicon structure, bypassing TIMs for near-zero thermal impedance. At the heart of this technology is the Si-Integrated Micro Cooler, a silicon-based solution fusion-bonded to the chip’s backside. Demonstrated on a 3.3X-reticle CoWoS®-R package—a massive ~3,300 mm² interposer supporting multiple logic dies and HBM stacks—the system achieves junction-to-ambient thermal resistance (θJA) as low as 0.055 °C/W at a coolant flow rate of 40 ml/s. This outperforms lidded liquid cooling with TIMs (0.064 °C/W) by nearly 15%, enabling sustained operation at over 2.6 kW TDP with a temperature delta under 63°C.

CoWoS®  is TSMC’s flagship 2.5D packaging technology, pivotal for AI giants like NVIDIA’s GPUs and AMD’s Instinct accelerators. It stacks chips on a silicon interposer for ultra-high interconnect density, supporting up to 12 HBM4 stacks in future “Super Carrier” iterations spanning 9 reticles. However, as interposers scale to 2,500 mm² or larger, heat flux intensifies, risking electromigration and yield loss. The IMC-Si integrates seamlessly into CoWoS®-R and upcoming CoWoS®-L variants, which incorporate backside power delivery networks (BSPDN) and embedded deep trench capacitors (eDTCs) for enhanced power stability. Microchannel designs—featuring square pillars, trenches, or flat planes—optimize fluid dynamics, with pillar structures proving superior for turbulent flow and heat extraction.

The demonstration highlights practical viability. TSMC tested prototypes with deionized water as coolant, achieving power densities exceeding 7 W/mm² on logic chip backsides. Fusion bonding ensures hermetic seals, preventing leaks in high-pressure environments, while low-temperature processes maintain compatibility with 1.6nm-class nodes. Early results show no degradation in electrical performance, with signal integrity preserved across hybrid bonding interfaces.

This breakthrough extends beyond cooling; it’s a cornerstone of TSMC’s 3DFabric ecosystem, aligning with “More than Moore” strategies like hybrid bonding and CMOS 2.0. By eliminating TIMs, it reduces assembly costs and variability, while enabling trillion-transistor monolithic-like systems. For data centers, it slashes rack-level power—potentially halving cooling infrastructure needs—and supports immersion-compatible designs. In edge AI and 5G, compact IMC-Si modules could fit mobile HPC, boosting efficiency in autonomous vehicles and AR/VR.

Challenges remain: scaling microfluidic fabrication to high volumes, ensuring coolant purity to avoid corrosion, and integrating with emerging materials like silicon carbide interposers for even higher thermal conductivity. Yet, TSMC’s track record—powering 80% of advanced AI chips—positions it to lead commercialization by 2027.

Dr. Kevin Zhang, TSMC’s Deputy Co-COO and Senior Vice President, emphasized: “Direct-to-Silicon Liquid Cooling breaks the thermal wall, unlocking the full potential of CoWoS® for exascale AI. This isn’t just incremental; it’s transformative for sustainable computing.”

As AI workloads explode, TSMC’s innovation heralds a cooler, greener future for semiconductors, where heat is no longer the limiter but a solved equation.

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Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award
by Daniel Nenni on 10-06-2025 at 10:00 am
Categories: Chiplet, Events, Foundries, TSMC

TSMC 3D Fabric Packaging TSMC OIP 2025

In a significant milestone for the semiconductor industry, Teradyne was honored as the 2025 TSMC Open Innovation Platform® Partner of the Year for TSMC 3DFabric® Testing. This award, announced on September 25, 2025, underscores the deep collaboration between Teradyne, a leader in automated test equipment and robotics, and TSMC, the world’s premier semiconductor foundry. The recognition highlights their joint efforts in advancing multi-die test methodologies for chiplets and TSMC’s CoWoS® advanced packaging technology, marking a pivotal step in the shift toward chiplet-based architectures essential for AI and high-performance computing.

Teradyne, headquartered in North Reading, Massachusetts, specializes in designing and manufacturing automated test solutions for semiconductors, electronics, and robotics systems. Its portfolio ensures high-quality performance across complex devices, from wafer-level testing to final assembly. TSMC dominates the foundry market with cutting-edge process nodes and packaging innovations. The partnership traces back to at least 1999, when TSMC adopted Teradyne’s automatic test equipment for 0.18-micron test chips. Over the years, this alliance has evolved, with Teradyne contributing to TSMC’s ecosystem through innovations in test strategies for heterogeneous integration.

At the heart of this award is TSMC’s OIP, launched in 2008 to foster collaboration among design partners, IP providers, and ecosystem members. OIP accelerates innovation by integrating process technology, EDA tools, and IP, enabling faster implementation of advanced designs. Celebrating its 15th anniversary in 2023, OIP has grown from 65nm nodes onward, addressing rising design complexities. Within this framework, the 3DFabric Alliance, introduced in 2023, focuses on overcoming challenges in 3D integration and advanced packaging.

TSMC 3DFabric® represents a comprehensive suite of 3D silicon stacking and advanced packaging technologies, encompassing both 2.5D and 3D architectures like CoWoS and InFO. These enable heterogeneous integration, boosting system-level performance, power efficiency, and form factors for applications in AI accelerators, 5G, and HPC. CoWoS, in particular, supports multi-die packages by stacking chips on silicon interposers, ideal for demanding AI workloads.

Through the 3DFabric Alliance, Teradyne and TSMC have pioneered test methodologies that enhance silicon bring-up efficiency and test quality. Teradyne’s investments in UCIe, GPIO, and streaming scan test solutions facilitate scalable, high-quality testing of die-to-die interfaces. UCIe, an open standard for chiplet interconnects, ensures seamless data transfer between dies, while streaming scan enables high-speed testing over these interfaces at wafer sort or probing stages. This reduces defect escapes, lowers quality costs, and accelerates time-to-market for 3D ICs used in AI and cloud datacenters.

Shannon Poulin, President of Teradyne’s Semiconductor Test Group, emphasized the value of TSMC’s collaborative ecosystem: “At Teradyne, we strongly believe in the open and collaborative ecosystem approach of TSMC’s Open Innovation Platform and look forward to continuing our partnership to drive innovation and deliver exceptional value to our customers.” Aveek Sarkar, Director of TSMC’s Ecosystem and Alliance Management Division, congratulated Teradyne, noting their contributions to improving silicon bring-up and enabling AI proliferation through energy-efficient compute.

The award was unveiled at the 2025 TSMC North America OIP Ecosystem Forum in Santa Clara, California, on September 24, 2025. This event gathered industry leaders to explore AI’s role in next-generation designs for TSMC’s advanced nodes like A16, N2, and N3. Highlights included discussions on AI-accelerated chip design, multi-die systems, and 3DFabric advancements, with partners showcasing tools for HPC and energy efficiency.

This partnership not only strengthens Teradyne’s position in AI hardware testing but also propels the industry toward more efficient, scalable semiconductor solutions. As demand for AI and cloud infrastructure surges, collaborations like this will be crucial in shortening development cycles and enhancing reliability. Looking ahead, Teradyne and TSMC’s ongoing innovations promise to redefine heterogeneous integration, driving the next wave of technological breakthroughs

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Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms

Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms
by Daniel Nenni on 10-06-2025 at 6:00 am
Categories: Events, Foundries, TSMC

Sofics TSMC OIP 2025 SemiWiki

In the fast-evolving semiconductor landscape, electrostatic discharge (ESD) protection is pivotal for ensuring chip reliability amid shrinking nodes and extreme applications. Sofics, a Belgian IP provider specializing in ESD solutions for ICs, has cemented its leadership through strategic collaborations showcased at TSMC’s 2025 Open Innovation Platform Ecosystem Forum. By delivering Power-Performance-Area optimized ESD IP across TSMC nodes from 250nm to 2nm, Sofics enables innovations in AI infrastructure and harsh-environment electronics.

A prime example is Sofics’ partnership with Celestial AI, tackling AI’s “memory wall” bottleneck. As AI models explode in size—410x every two years for Transformers—compute FLOPS have scaled 60,000x over 20 years, but DRAM bandwidth lags at 100x and interconnects at 30x, wasting cycles on data movement. Celestial AI’s Photonic Fabric™ revolutionizes this with optical interconnects, delivering data directly to compute points for superior bandwidth density, low latency, and efficiency. Traditional optics demand DSPs and re-timers, inflating power and latency, but Photonic Fabric uses linear-drive optics, eliminating DSPs via high-SNR modulators and grating couplers.

Sofics customized ESD IP for TSMC’s 5nm process, proven in production, to protect Photonic Fabric’s sensitive interfaces. Tx/Rx circuits operate at ~1V with <20fF parasitic capacitance for 50-100Gbps signals, ensuring signal integrity while fitting dense packaging. ESD ratings hit 50V CDM with <100nA leakage, supporting thin-oxide circuits without GPIO cells. Power clamps handle non-standard voltages (1.2V-3.3V) in small areas, vital for EIC-PIC integration. This collaboration, highlighted at OIP, breaks bandwidth barriers, enabling multi-rack AI scaling. Celestial AI’s August 2025 Photonic Fabric Module, a TSMC 5nm MCM with PCIe 6/CXL 3.1, exemplifies this, backed by $255M funding.

Equally groundbreaking is Sofics’ alliance with Magics Technologies, enabling radiation-hardened (rad-hard) ICs for nuclear, space, aerospace, and medical sectors. Demand surges for rad-hard electronics amid space exploration and nuclear fusion research like ITER, where ICs must endure >1MGy TID and >62.5 MeV·cm²/mg SEE without malfunction. Magics, a Belgian firm with 10+ years in rad-hard-by-design, offers chips like wideband PLLs (1MHz-3GHz, -99dBc/Hz phase noise) and series for motion, imaging, time, power, and AI processing.

Sofics provides rad-hard ESD clamps for Magics’ TSMC CMOS designs, supporting voltages like 1.2V/3.3V with >2kV HBM, <20nA leakage, and <1700um² area. Key features include cold-spare interfaces (latch-up immune, SEE-insensitive up to 80MeV·cm²/mg) and stacked thin-oxide devices for 1.2V GPIOs on 28nm, bypassing thick-oxide limitations. This 15-year TSMC-Sofics tie, via IP & DCA Alliances, ensures early access and quality. Magics’ €5.7M funding in April 2025 accelerates commercialization.

Bottom line: These partnerships underscore TSMC’s ecosystem strength, with Sofics supporting 90+ customers in AI/datacenters (40+ projects) and space (e.g., Mars rover, CERN). By optimizing ESD for photonics and rad-hard apps, Sofics drives innovation, from hyperscale AI to fusion reactors, proving ESD IP’s role in overcoming physical limits.

Fore more information contact Sofics

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Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation
by Daniel Nenni on 10-01-2025 at 10:00 am
Categories: EDA, Events, Foundries, Synopsys, TSMC

UNDER EMBARGO 1PM PT Sept 24 Synopsys TSMC OIP 2025 (1)

In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages Synopsys’ EDA tools and IP solutions alongside TSMC’s cutting-edge processes and packaging technologies. The result? Accelerated innovation that empowers chip designers to create high-performance, low-power multi-die architectures essential for next-generation AI applications, from data centers to edge devices, absolutely.

At the heart of this alliance is Synopsys’ commitment to enabling differentiated designs on TSMC’s advanced nodes. Certified digital and analog flows, integrated with Synopsys.ai, are now available for TSMC’s N2P and A16 processes, incorporating the innovative NanoFlex architecture. This setup not only boosts performance but also streamlines analog design migration, allowing engineers to scale chips efficiently while optimizing power consumption. For the A16 node, Synopsys has enhanced capabilities for Super Power Rail (SPR) designs, improving power distribution and thermal management in backside routing. Additionally, pattern-based pin access methodologies have been refined to deliver superior area efficiency. Looking ahead, the duo is already collaborating on flows for TSMC’s A14 process, with the first process design kit slated for release later in 2025.

Physical verification is equally robust, with Synopsys’ IC Validator certified for A16, supporting design rule checking (DRC) and layout versus schematic (LVS) verification. Its elastic architecture handles complex electrostatic discharge (ESD) rules on N2P with faster turnaround times, ensuring reliability in high-stakes AI systems.

A standout feature of the collaboration is the focus on 3D integration, addressing the limitations of traditional 2D scaling. Synopsys’ 3DIC Compiler platform, a unified exploration-to-signoff tool, supports TSMC’s SoIC-X technology for 3D stacking, as well as CoWoS packaging for silicon interposers and bridges. This has facilitated multiple customer tape-outs, demonstrating real-world success. The platform automates critical tasks like UCIe and HBM routing, through-silicon via (TSV) planning, bump alignment, and multi-die verification, slashing design cycles and enhancing productivity. In photonics, an AI-optimized flow for TSMC’s Compact Universal Photonic Engine (COUPE) tackles multi-wavelength operations and thermal challenges, boosting system performance in optical interconnects vital for AI data transfer.

Complementing these EDA advancements is Synopsys’ expansive IP portfolio, optimized for TSMC’s N2/N2P nodes to minimize power usage and integration risks. It includes high-performance interfaces like HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, alongside automotive-grade solutions for N5A and N3A processes. This suite—encompassing PHYs, embedded memories, logic libraries, programmable I/O, and non-volatile memory—ensures safety, security, and reliability across markets like automotive, IoT, and high-performance computing (HPC). For multi-die designs, specialized 3D-enabled IP further accelerates silicon success.

I spoke with Michael Buehler-Garcia, Senior Vice President at Synopsys at the event. He is a long time friend. He emphasized the partnership’s impact:

Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry’s most advanced packaging and process technologies,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC’s advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.”

Echoing this, Aveek Sarkar, Director of TSMC’s Ecosystem and Alliance Management Division, highlighted the ecosystem’s role:

“TSMC has been working closely with our long-standing Open Innovation Platform® (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs,”.

“With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets.”

Bottom Line: This synergy positions Synopsys and TSMC at the forefront of the AI revolution, where multi-die systems promise to overcome Moore’s Law bottlenecks by integrating heterogeneous dies for superior efficiency. As AI workloads explode, such innovations will reduce energy footprints in hyperscale data centers and enable smarter autonomous vehicles.

Also Read:

Synopsys Announces Expanding AI Capabilities and EDA AI Leadership

AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions

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Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025
by Daniel Nenni on 10-01-2025 at 6:00 am
Categories: Alchip, Chiplet, Events, Foundries, Semiconductor Services, TSMC

Alchip TSMC OIP 2025

In the relentless race to power next-generation artificial intelligence (AI) systems, data connectivity has emerged as the critical bottleneck. As AI models balloon in size—from billions to trillions of parameters—compute resources alone are insufficient. According to Ayar Labs, approximately 70% of AI compute time is wasted waiting for data, a inefficiency that escalates exponentially with system scale. Traditional copper-based electrical I/O, while reliable for intra-rack connections, falters under the demands of multi-rack AI clusters. Power consumption soars, latency spikes, and bandwidth caps out, rendering electrical solutions obsolete for hyperscale datacenters. Enter the strategic collaboration between Alchip Technologies and Ayar Labs, unveiled in September 2025, which promises to shatter these barriers through co-packaged optics (CPO) and advanced packaging innovations.

At the TSMC North America Open Innovation Platform (OIP) Ecosystem Forum on September 26, the partnership fuses Alchip’s expertise in high-performance ASIC design and 2.5D/3D packaging with Ayar Labs’ pioneering optical I/O chiplets. This isn’t mere integration; it’s a holistic ecosystem leveraging TSMC’s COUPE (Co-packaged Optics with Unified Packaging and Electronics) technology to embed optical engines directly onto AI accelerator packages. The result? A reference design platform that enables seamless, multi-rack scale-up networks, transforming AI infrastructure from rigid, power-hungry monoliths into flexible, composable architectures.

At the heart of this solution lies Ayar Labs’ TeraPHY™ optical engines, silicon photonics-based chiplets that replace cumbersome pluggable optics with in-package optical I/O. Each TeraPHY engine employs a stacked Electronic Integrated Circuit (EIC) and Photonic Integrated Circuit (PIC) architecture, utilizing microring modulators for dense, efficient light-based data transmission. The EIC, fabricated on advanced nodes, handles protocol-specific features like UCIe-A (Universal Chiplet Interconnect Express-Advanced) for logic protocols such as CHI, while the PIC manages optical signaling. A detachable optical connector simplifies manufacturing, assembly, and testing, ensuring high-volume scalability. Protocol-agnostic by design, TeraPHY supports endpoints like UALink, PCIe, and Ethernet, with forward error correction (FEC) and retimer logic delivering raw bit error rates below 10^-6 for PAM4 CWDM optics—achieving single-hop latencies of 100-200 nanoseconds. Future DWDM variants promise even lower 20-30 ns latencies and BERs under 10^-12.

Alchip complements this with its I/O protocol converter chiplets, bridging UCIe-A (streaming mode) to scale-up protocols, and integrated passive devices (IPDs) that optimize signal integrity through custom capacitors. Their prototype, showcased at Booth 319 in Taipei and Silicon Valley, integrates two full-reticle AI accelerators, four protocol converters, eight TeraPHY engines, and eight HBM stacks on a common substrate. This configuration unlocks over 100 Tbps of scale-up bandwidth per accelerator and more than 256 optical ports, dwarfing electrical I/O’s limits. Power density remains manageable, as optics reduce end-to-end energy per bit by minimizing electrical trace lengths and avoiding the thermal overhead of pluggables.

The implications for AI workloads are profound. In scale-up networks, where XPUs (AI processing units) must act as unified entities—scaling from 100 to 1,000 units—the joint solution enables XPU-to-XPU, XPU-to-switch, and switch-to-switch connectivity with path diversity for ultra-low latency. Extended memory hierarchies, pooling DRAM across racks via optical links, boost application metrics like training throughput by 2-3x, per preliminary simulations. Energy efficiency improves dramatically: Optical I/O consumes up to 10x less power than copper equivalents, critical as AI racks approach 100kW densities. For hyperscalers like those deploying GPT-scale models, this means greener, more interactive datacenters capable of real-time inference at exascale.

This collaboration underscores a broader industry shift toward disaggregated, photonics-driven computing. By addressing reach limitations beyond copper’s 1-2 meter horizon and enhancing radix for massive parallelism, Alchip and Ayar Labs are not just solving today’s challenges but future-proofing AI. As Vladimir Stojanovic, Ayar Labs’ CTO and co-founder, notes, “AI has reached an inflection point where traditional interconnects limit performance, power, and scalability.” Erez Shaizaf, Alchip’s CTO, echoes this, emphasizing the need for “innovative, collaborative advanced packaging.” With production-ready test programs and reliability qualifications, the duo is poised to accelerate adoption, potentially slashing AI deployment costs by 30-50% through efficiency gains.

Bottom line: This partnership heralds a new era of AI infrastructure: scalable, flexible, and composable. As models grow unabated, optical CPO will be indispensable, and Alchip-Ayar Labs’ blueprint offers a proven path forward. Hyperscalers take note—this is the optics revolution AI has been waiting for.

Contact Alchip

Also Read:

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation

Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap

Alchip’s Technology and Global Talent Strategy Deliver Record Growth

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Analog Bits Steps into the Spotlight at TSMC OIP

Analog Bits Steps into the Spotlight at TSMC OIP
by Mike Gianfagna on 09-29-2025 at 10:00 am
Categories: Analog Bits, Events, Foundries, IP, TSMC

Analog Bits Steps into the Spotlight at TSMC OIP

The TSMC Open Innovation Platform (OIP) Ecosystem Forum kicked off on September 24 in Santa Clara, CA. This is the event where TSMC recognizes and promotes the vast ecosystem the company has created. After watching this effort grow over the years, I feel that there is nothing the group can’t accomplish thanks to the alignment and leadership provided by TSMC. Some ecosystem members are new and are finding their place in the organization. Others are familiar names who have provided consistent excellence over the years. Analog Bits is one of the companies in this latter category. Let’s examine what happens when Analog Bits steps into the spotlight at TSMC OIP.

What Was Announced, Demonstrated and Discussed

Analog Bits always arrives at industry events like this with exciting news about new IP and industry collaboration. At TSMC OIP, the company announced its newest LDO, power supply droop detectors, and embedded clock LC PLL’s on the TSMC N3P process.  Clocking, high accuracy PVT, and droop detectors were also announced on the TSMC N2P process.

Here is a bit of information about these fully integrated IP titles:

  • The scalable LDO (low drop-out) regulator macro addresses typical SoC power supply and other voltage regulator needs.
  • The droop detector macro addresses SoC power supply and other voltage droop monitoring needs. It includes an internal bandgap style voltage reference circuit which is used as a trimmed reference to compare the sampled voltage against.
  • The PVT sensor is a highly integrated macro for monitoring process, voltage, and temperature on chip, allowing very high precision even in untrimmed usage. The device consumes very little power even in operational mode, and leakage power only when temperature measurement is complete.
  • The PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation.

These announcements were also backed up with live demonstrations in the Analog Bits booth at the show. The demos included:

  • High accuracy PVT sensors, high performance clocks, droop detectors, and more on the TSMC N2P process
  • Programmable LDO, droop detector, high accuracy sensors, low jitter LC PLL and more on the TSMC N3P process
  • Automotive grade pinless high accuracy PVT, pinless PLL, PCIe SERDES on the TSMC N5A process
Analog Bits booth at TSMC OIP

Analog Bits also participated in the technical program at OIP with two joint papers. 

One with Socionext titled “Pinless PLL, PVT Sensor and Power Supply Spike Detectors for Datacenter, AI and Automotive Applications”.

The other was with Cerebras titled “On-Die Power Management for SoCs and Chiplet” at the virtual event.

While discussing Analog Bits’ new intelligent energy and power management strategy, Mahesh Tirupattur, CEO at Analog Bits commented:

“Whether you are designing advanced datacenters, AI/ML applications, or automotive SoC’s, managing power is no longer an afterthought, it has to be done right at the architectural phase or deal with the consequences of not doing so . We have collaborated with TSMC and trailblazed on our IP development with advanced customers to pre-qualify novel power management IP’s such as LDO, droop detectors, and high-accuracy sensors along with our sophisticated PLL’s for low jitter. We welcome customers and partners to see our latest demos at the Analog Bits booth during this year’s TSMC OIP event.”

Recognition

TSMC also recognizes outstanding achievement by its ecosystem partners with a series of awards that are announced at the show. For the second year in a row, Analog Bits received the 2025 OIP Partner of the Year Award from TSMC in the Analog IP category for enabling customer designs with broad portfolio of IPs to accelerate design creation. This is quite an accomplishment. Pictured at the right is Mahesh Tirupattur receiving the award at OIP.

Mahesh also created a short video for the TSMC event. In that video, he discusses the significance of the collaboration with TSMC, not just in 2025 but over the past two decades. He talks about the age of AI explosion, and the focus Analog Bits has to deliver safe, reliable, observable and efficient power. He talks about the benefits of delivering advanced low power mixed signal IP on TSMC’s 2 and 3 nm technologies. It’s a great discussion, and you can now view it here.

To Learn More

You can learn more about what Analog Bits is doing around the industry on SemiWiki here. You can begin exploring the billions of IP solutions Analog Bits has delivered on the company’s website here.  The TSMC Open Innovation Platform Ecosystem Forum will be held in other locations around the world. Analog Bits will be attending as well. You can learn more about this important industry event here.  And that’s what happens when Analog Bits steps into the spotlight at TSMC OIP.