TSMC vs Intel Foundry vs Samsung Foundry 2026

TSMC vs Intel Foundry vs Samsung Foundry 2026
by Daniel Nenni on 02-13-2026 at 6:00 am

TSMC vs Intel Foundry vs Samsung Foundry

The global semiconductor industry sits at the foundation of modern technology, powering everything from smartphones and cloud data centers to artificial intelligence, automobiles, and national defense systems. At the center of advanced chip manufacturing are three major players: TSMC, Samsung Foundry, and Intel Foundry. Each represents a distinct manufacturing model and strategic philosophy, and together they form a competitive landscape that is essential for innovation, resilience, and long-term industry health.

TSMC is the undisputed leader in pure-play foundry manufacturing. By focusing exclusively on manufacturing and avoiding competition with its customers in chip design, TSMC has built deep trust with fabless companies such as Nvidia, AMD, Apple, and Qualcomm. This focus has allowed TSMC to lead in process technology, consistently delivering the most advanced nodes such as N5, N3, and the upcoming N2 with strong yields and predictable execution. Its dominance has been especially visible in the AI era, where advanced nodes and packaging technologies like CoWoS have become critical bottlenecks.

Samsung Foundry represents a vertically integrated alternative. As part of Samsung Electronics, it both manufactures chips and designs its own products, including memory, logic, and consumer devices. Samsung has pushed aggressively into leading-edge nodes such as 2nm using gate-all-around (GAA) transistors and continues to invest heavily in advanced packaging and U.S. manufacturing. While Samsung has faced significant challenges in yield consistency compared to TSMC they routinely undercut TSMC wafer pricing. It is hard to figure out the math on that point. Even so, Samsung’s presence provides customers with an important second source at advanced nodes.

Intel Foundry is the most strategically significant entrant into the modern foundry race. Historically a vertically integrated company that designed and manufactured its own chips, Intel is opening its leading edge fabs to external customers while rebuilding its process leadership. Intel’s roadmap includes advanced nodes such as Intel 18A, as well as differentiated capabilities in advanced packaging (EMIB, Foveros) with U.S. based manufacturing. While Intel Foundry is still in the initial stages of winning major external customers, its success would meaningfully rebalance the industry by adding large-scale leading-edge capacity inside the United States.

Competition among these three players is not merely a commercial or political issue, it is structurally critical for the semiconductor ecosystem.

First, competition drives technological progress. Advanced chip manufacturing requires enormous capital investment, deep engineering talent, and long development cycles. Without competitive pressure, there would be less incentive to take risks on new transistor architectures, materials, or manufacturing techniques. The rapid evolution from FinFETs to GAAFET transistors is a direct result of competitive urgency.

Second, competition improves supply-chain resilience. Semiconductors are now a matter of national and economic security. Over-reliance on a single foundry or region increases vulnerability to geopolitical tensions, natural disasters, and capacity shocks. A competitive landscape with strong players in different regions reduces single-point-of-failure risk for governments and industries alike.

Third, customers benefit from choice and leverage. Fabless chip designers depend on foundries not just for wafers, but for co-optimization across design, packaging, and manufacturing. When customers have alternatives, they gain negotiating power on pricing, capacity allocation, and long-term roadmap alignment. This keeps foundries responsive to customer needs rather than dictating terms.

Finally, competition fuels ecosystem growth. Foundries anchor vast networks of equipment suppliers, materials companies, EDA vendors, and OSAT partners. When multiple foundries invest aggressively, the entire ecosystem advances faster, benefiting innovation well beyond any single company.

Bottom line: TSMC, Samsung Foundry, and Intel Foundry are not redundant competitors they are essential counterweights. The semiconductor industry needs all three to succeed, because competition ensures innovation, resilience, and sustainable growth in one of the most strategically important industries in the world, absolutely,

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TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce

TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce
by Daniel Nenni on 02-08-2026 at 2:00 pm

TSMC GCU Semiconductor Training Program

The expansion of semiconductor manufacturing in the United States, particularly with TSMC’s multi-fab campus in Phoenix, Arizona, has created a significant need for skilled technical workers. To meet this demand, TSMC has partnered with educational institutions, including Grand Canyon University (GCU), to launch innovative training pathways aimed at preparing individuals for careers in semiconductor fabrication and operations. This partnership is part of a broader ecosystem effort involving government, workforce boards, community colleges, and universities working together to develop a sustainable talent pipeline for the semiconductor industry.

Why the Program Exists

Semiconductor manufacturing is one of the most technically demanding and high-technology sectors in the global economy. Operating advanced fabrication facilities, or “fabs”, requires talent with specialized skills in automated systems, precision processes, cleanroom operations, and semiconductor science. When TSMC announced its Arizona investment, one of the key challenges highlighted was the shortage of locally available semiconductor workforce talent with requisite technical skills. In response, the company and regional partners have collaborated on training and apprenticeship programs to build that talent ecosystem locally.

Program Structure and Partnerships

The TSMC-GCU semiconductor training program, formally known as the Manufacturing Specialist Intensive Pathway, is an industry-aligned educational pathway created to prepare participants for technical roles within semiconductor manufacturing. This initiative is part of a broader suite of workforce development efforts that also include registered apprenticeship programs, technician training with community colleges and Northern Arizona University, and other industry partnerships.

At its core, the program with Grand Canyon University focuses on equipping individuals with practical skills that map directly to Manufacturing Specialist roles at TSMC’s Phoenix fabs. The curriculum encompasses semiconductor fundamentals, wafer fabrication processes, standard operational procedures, and factory-floor workflows, all of which are foundational knowledge areas for anyone seeking to enter semiconductor manufacturing.

Program Details

Duration & Format: The program typically runs over a 15-week period, blending classroom instruction with industry-relevant learning experiences designed to mirror real semiconductor manufacturing environments.

Credentialing: Participants earn a certificate of completion from GCU, along with 16 college credit hours, and industry-recognized professional credentials from the Institute of Electrical and Electronics Engineers (IEEE), which helps validate competencies to employers.

Target Audience: The training is geared toward a wide range of learners — from high school graduates and career changers to individuals already in the workforce seeking new tech-focused opportunities.

Pathway to Employment: Successful participants gain not only educational credentials but also a competitive advantage when applying for semiconductor technician, manufacturing specialist, or related technical roles at TSMC or other semiconductor firms in Arizona.

Broader Workforce Strategy

While the GCU partnership is a key piece of the talent development puzzle, it sits within a larger regional workforce strategy. TSMC’s Registered Technician Apprenticeship program, supported by the State of Arizona, the City of Phoenix, and institutions like Estrella Mountain Community College, Northern Arizona University, and other partners, offers multi-year apprenticeship pathways in equipment, process, and facilities technician roles that combine classroom instruction with paid on-the-job training.

These programs are designed to address both entry-level and advanced technical needs. Apprentices typically work hands-on in real semiconductor environments while earning credit and experience, which can lead to stackable credentials and even associate or bachelor’s degrees when combined with college coursework.

Impact and Future Prospects

The TSMC-GCU semiconductor training program underscores the importance of public-private educational collaboration in scaling a skilled workforce fast enough to match the pace of industrial growth. By equipping participants with relevant technical knowledge and credentials recognized by both academia and industry, the program not only fills immediate labor gaps but also fosters long-term career opportunities in a high-tech sector that is becoming increasingly critical for U.S. competitiveness.

Bottom line: This initiative helps bridge the transition from education to employment in a field where the demand for skilled workers is projected to grow as semiconductor manufacturing continues to expand across the United States.

CONTACT GCU

CONTACT TSMC

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NanoIC Extends Its PDK Portfolio with First A14 Logic and eDRAM Memory PDK

NanoIC Extends Its PDK Portfolio with First A14 Logic and eDRAM Memory PDK
by Daniel Nenni on 02-04-2026 at 6:00 am

Nano IC TSMC Process Roadmap

NanoIC has announced a major expansion of its process design kit portfolio with the introduction of its first A14 logic and embedded eDRAM  memory PDK. This milestone reflects the company’s growing role in enabling advanced semiconductor design at cutting-edge technology nodes and addresses increasing industry demand for highly integrated, power-efficient system-on-chip (SoC) solutions.

As semiconductor processes continue to scale, the availability of robust and well-validated PDKs has become a critical success factor for chip designers. A PDK serves as the essential interface between a foundry’s manufacturing process and EDA tools, providing accurate models, design rules, device libraries, and verification decks. By extending its portfolio to include A14-class technology, NanoIC is positioning itself to support next-generation designs for applications such as AI, HPC, mobile processors, and advanced networking.

The newly released A14 logic PDK is designed to address the challenges associated with extreme scaling, including tighter design rules, increased variability, and complex power-performance trade-offs. NanoIC’s solution offers comprehensive transistor models, standard cell support, and reliability data that allow designers to confidently optimize performance, power consumption, and silicon area. This is especially important at advanced nodes, where even small inaccuracies in modeling can lead to costly redesigns or yield issues.

What sets this announcement apart is the inclusion of an eDRAM memory PDK alongside the logic offering. Embedded DRAM has re-emerged as an attractive memory option for advanced SoCs due to its higher density compared to SRAM and lower latency compared to off-chip DRAM. Integrating eDRAM directly on logic chips enables designers to build memory-rich architectures that improve bandwidth and energy efficiency, key requirements for data-intensive workloads such as AI inference and edge computing.

NanoIC’s A14 eDRAM PDK provides designers with the tools needed to seamlessly integrate memory blocks into complex SoC designs. The PDK includes memory cell libraries, timing and power models, and process-aware design rules that ensure manufacturability and reliability. By aligning the eDRAM PDK closely with the A14 logic process, NanoIC enables tighter co-optimization between logic and memory, reducing design complexity and accelerating time-to-market.

Another important aspect of the new PDKs is their compatibility with leading EDA platforms. NanoIC has emphasized interoperability and early design enablement, allowing customers to begin architectural exploration and IP development well before volume manufacturing. This early access is increasingly valuable as design cycles lengthen and the cost of advanced-node development continues to rise.

From a broader industry perspective, NanoIC’s move highlights a growing trend toward specialized and differentiated PDK offerings. As advanced nodes become more complex, chipmakers are seeking partners that can provide deep process expertise and tailored design enablement rather than one-size-fits-all solutions. By delivering both logic and eDRAM PDKs at the A14 level, NanoIC demonstrates its ability to support heterogeneous integration and memory-centric architectures that define modern semiconductor innovation.

Bottom line: NanoIC’s extension of its PDK portfolio with its first A14 logic and eDRAM memory PDK represents a significant step forward for the company and its customers. The new offerings address the technical demands of advanced semiconductor design while enabling higher performance, greater integration, and improved power efficiency. As the industry continues to push the limits of scaling and system complexity, comprehensive PDK solutions like NanoIC’s will play a crucial role in turning ambitious chip concepts into manufacturable reality.

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TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor Innovation

TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor Innovation
by Daniel Nenni on 02-02-2026 at 8:00 am

TSMC AZ Day FAB 21

In February of 2026, Taiwan Semiconductor Manufacturing Company (TSMC) will host the TSMC AZ Exclusive Experience Day in Phoenix, Arizona, offering selected participants a rare opportunity to engage directly with one of the most advanced semiconductor manufacturing organizations in the world. The event will serve as an immersive introduction to TSMC’s Arizona operations, highlighting the company’s culture, technological leadership, and long-term commitment to building a robust U.S. semiconductor ecosystem.

Designed as more than a traditional recruitment event, the Exclusive Experience Day will provide attendees with an in-depth look at what it means to work at the forefront of advanced chip manufacturing. Participants will gain insight into TSMC’s operational philosophy, engineering rigor, and collaborative environment through curated presentations, interactive sessions, and direct engagement with company leaders and engineers. By opening its doors to a select audience, TSMC will aim to foster meaningful connections with future talent while communicating its expectations for excellence, discipline, and innovation.

The event will take place against the backdrop of TSMC’s rapidly expanding Arizona presence. As the company continues its multi-billion-dollar investment in advanced fabrication facilities in the state, Arizona is expected to become a cornerstone of U.S.-based semiconductor manufacturing. These fabs will play a critical role in supporting industries such as artificial intelligence, high-performance computing, automotive electronics, and advanced mobile devices. The Exclusive Experience Day will therefore not only introduce career opportunities but also contextualize how individual roles contribute to broader national and global technology goals.

Throughout the day, attendees will have opportunities to interact with TSMC engineers, technicians, managers, and human resources professionals. These interactions will allow participants to ask detailed questions about career paths, training programs, work expectations, and life inside a high-tech semiconductor fab. By facilitating candid conversations, TSMC will seek to demystify the realities of semiconductor manufacturing and help prospective employees assess alignment between their skills, aspirations, and the company’s mission.

A key feature of the experience will be guided exposure to fab operations and environments. Participants will learn about cleanroom protocols, advanced process technologies, and the precision required to manufacture chips at nanometer scales. For many attendees, this will be their first opportunity to understand the discipline and teamwork required to operate within one of the world’s most sophisticated manufacturing settings. This hands-on exposure will reinforce the idea that semiconductor manufacturing is both technically demanding and deeply collaborative.

Beyond technical learning, the 2026 TSMC AZ Exclusive Experience Day will emphasize culture and community. TSMC will present its core values, including long-term thinking, continuous improvement, and mutual trust, while also highlighting its investment in employee development and local engagement. As the company continues to integrate into the Arizona community, workforce development and talent cultivation will remain central to its strategy. Events like this will help build a shared sense of purpose between TSMC and the people who will support its operations for decades to come.

The timing of the event will align with ongoing hiring and workforce expansion efforts, making it especially relevant for students, early-career professionals, and experienced engineers seeking to participate in a once-in-a-generation manufacturing build-out. For attendees, the experience will offer clarity on expectations, opportunity, and impact, providing a realistic and inspiring view of what a career at TSMC Arizona could entail.

Bottom line:  the 2026 TSMC AZ Exclusive Experience Day will represent more than an introduction to jobs or facilities. It will serve as an invitation to join a transformative effort in advanced manufacturing, where individual talent and global technology leadership intersect. By bringing future employees inside its vision, TSMC will reaffirm that the success of the semiconductor industry depends not only on capital and equipment, but on the people who design, build, and sustain it.

CONTACT TSMC

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The Foundry Model Is Morphing — Again

The Foundry Model Is Morphing — Again
by Jonah McLeod on 01-29-2026 at 10:00 am

SIP Market

When Morris Chang left Texas Instruments in 1983 to found TSMC, he was not merely starting a new company—he was proposing a new industrial logic. Chang recognized that semiconductor manufacturing had become so capital-intensive that it could no longer survive as just one function inside a vertically integrated company. His answer was radical for its time: specialize. Let foundries manufacture, let fabless companies design, and let scale economics determine who survives. Over the next four decades, that model reshaped the entire semiconductor industry.

But the conditions that made the pure-play foundry model dominant are changing again.

As process scaling slows, product lifetimes lengthen, and differentiation shifts away from raw transistor density, manufacturing alone is no longer sufficient to define competitive advantage—especially outside the consumer and cloud-compute markets. Increasingly, value is migrating up the stack, toward system enablement: hardened IP, software continuity, platform longevity, and predictable lifecycle support. In this environment, foundries are no longer just wafer suppliers. They are becoming infrastructure providers.

Seen in that light, GlobalFoundries’ recent acquisition of Synopsys’ CPU IP business—including the ARC processor family—marks something more significant than a portfolio expansion. It signals a second evolution of the foundry model itself. Where Morris Chang separated manufacturing from design to survive the economics of scaling, today’s foundries are selectively reintegrating high-value hard IP to survive the economics of maturity.

This is not a retreat to the IDM era. It is a recognition that in long-lifecycle markets—automotive, industrial, infrastructure, and embedded systems—customers increasingly demand platform certainty, not just wafers. The foundry model is not being abandoned. It is being adapted.

As traditional scaling economics weaken and capital intensity rises, competitive advantage—especially outside consumer and hyperscale compute—shifts from raw transistor density to lifecycle execution and design enablement. “In embedded and industrial markets, leading suppliers explicitly commit to 10–15+ year availability and continuity-of-supply, reflecting customer demand for long-lived platforms rather than frequent redesigns.”

At the same time, the semiconductor IP business has become a multi-billion-dollar market opportunity (roughly $7–8B annually, according to MarketsandMarkets), with the Asia Pacific region, predominately China, holding the largest share. Moreover, it is still growing, with recent industry tracking showing strong IP revenue acceleration. Foundries are responding by expanding from wafer output into “design infrastructure”—ecosystems of qualified IP, certified EDA flows, PDKs, DFM, packaging, and services—exemplified by programs like TSMC’s OIP. In that environment, foundries are no longer just wafer suppliers; they are becoming platform and infrastructure providers for whole product lifecycles.

A Foundry Built by Accumulation

GlobalFoundries did not arise from a single founding moment. It was assembled over time through a sequence of structural decisions, each responding to a different pressure in the semiconductor industry.

The process began in 2008–2009, when AMD spun off its manufacturing arm to escape the escalating capital demands of the IDM model. The move preserved AMD’s access to advanced production while freeing its design organization from an unsustainable cost structure.

That spinout would not have been possible without Mubadala Investment Company, which supplied the long-horizon capital and ownership stability AMD lacked. Mubadala ultimately took an 82% stake in the new foundry, insulating it from short-term financial pressures and enabling a strategy focused on durability rather than speed.

Mubadala then expanded GlobalFoundries’ footprint by acquiring Chartered Semiconductor in Singapore. This move transformed GF from an AMD carve-out into a geographically distributed foundry with real scale, adding multiple fabs, a diverse customer base, and specialty-process breadth.

The final foundational piece arrived in 2014, when IBM exited semiconductor manufacturing and transferred its East Fishkill and Essex Junction fabs—along with its advanced R&D organization and long-term POWER and Z supply agreements—to GlobalFoundries, even paying the company to assume the operations. This infusion of U.S. engineering talent and SOI-driven process technology elevated GF from a mid-range player to a foundry with world-class capabilities in specialized logic.

Taken together, these moves produced a company built by accumulation rather than invention: AMD contributed manufacturing DNA, Abu Dhabi provided capital and industrial patience, Chartered added global scale, and IBM delivered advanced technology. The result is a foundry whose strategy diverges sharply from firms built solely to chase leading-edge nodes. Ironically, AMD relies on TSMC for its leading edge FinFet process.

Two Electronics Universes

At the highest level, the global electronics industry has organized itself around two distinct competitive universes.

The first is consumer and cloud compute: smartphones, PCs, data centers, and hyperscale AI. This universe is driven by peak performance per watt, rapid product cycles, and relentless transistor density scaling. Capital intensity is extreme, product lifetimes are short, and a small number of customers account for a disproportionate share of demand. Manufacturing here has converged on a narrow set of players—TSMC foremost, with Samsung and Intel as the only credible peers at the leading edge.

The second universe, where GlobalFoundries squarely operates, is physical, embedded, and infrastructure electronics. This includes automotive systems, industrial automation, RF connectivity, power electronics, aerospace and defense, medical devices, energy systems, and embedded control and inference. Success in this universe is defined not by headline performance but by reliability, deterministic behavior, qualification, and supply continuity. Product lifetimes stretch over decades, not years.

Comparing GF to TSMC Misses the Point

TSMC, Samsung, and Intel compete in a three-player arena where scale, redundancy, and geopolitical resilience are existential requirements. Each new node demands tens of billions of dollars in capital investment, and the penalty for execution failure is severe.

GlobalFoundries deliberately exited this race. In doing so, it avoided the “middle squeeze” that eliminated many other foundries—companies that were neither large enough to win at the leading edge nor differentiated enough to command durable customers.

Instead, GF rebuilt around markets that value stability over novelty. Automotive, industrial, RF, power, and infrastructure customers do not want to requalify silicon every two years. They want predictability, long-term availability, and conservative process evolution. For these customers, a mature node that improves steadily over time is often more valuable than a bleeding-edge node with a short commercial half-life.

This is why GF appears to “sit by itself” while TSMC has Intel and Samsung as peers. That asymmetry reflects different market physics—not competitive weakness.

Process Innovation Without Density Obsession

Exiting the leading-edge race did not mean exiting process innovation. GlobalFoundries exited the transistor-density race, not the process-generation race that matters to its customers.

GF continues to advance performance, power efficiency, and reliability within existing nodes while evolving specialty platforms such as FD-SOI, RF-SOI, and power processes. These advances are often invisible in consumer-centric narratives, but they are decisive in automotive and industrial systems, where leakage, analog behavior, and qualification margins dominate real-world performance.

FD-SOI illustrates this philosophy particularly well. While it continues to scale geometrically, it does so on a different cadence and with different objectives than FinFET. Strong electrostatic control enables gains through body biasing, voltage scaling, and system integration, reducing pressure for aggressive geometry shrinks. This controlled evolution aligns naturally with long-lifecycle markets.

A Dual-Process Strategy by Design

A critical—and often overlooked—aspect of GlobalFoundries’ strategy is that it operates both FD-SOI and FinFET process families in volume. Unlike leading-edge foundries that concentrate almost exclusively on shrinking FinFET nodes, GF maintains two complementary process pillars optimized for different workloads and lifetimes.

FD-SOI platforms such as 22FDX and 28FD-SOI are optimized for ultra-low leakage, deterministic timing, and wide operating ranges, making them well suited for safety-critical, mixed-signal, and always-on domains. Mature FinFET nodes such as 12LP and 14LPP deliver higher performance for Linux-capable embedded systems, automotive domain controllers, and infrastructure silicon—without the churn of leading-edge scaling.

The coexistence of these platforms is not transitional; it is structural. Together, they allow GF to support a full spectrum of physical-world electronics without dependence on the 7-nm, 5-nm, or 3-nm race.

RISC-V and the Logic of Owning Compute IP

The strategic coherence of this model becomes clearer when viewed alongside the accelerating adoption of RISC-V. RISC-V’s fastest growth is occurring not in consumer compute, but in the same embedded, automotive, and industrial markets GF already serves.

Market estimates place the global RISC-V ecosystem at roughly $1.6–2.6 billion today, with projected growth of 25–33% CAGR, reaching $8–9 billion by 2030 and potentially $20–26 billion by the mid-2030s. While still small relative to Arm and x86, its trajectory is unmistakable.

GF’s acquisitions of MIPS and Synopsys’ ARC IP should be understood in this context. These moves anchor GF more deeply in the RISC-V ecosystem at the level that matters most: system enablement. ARC-V aligns naturally with FD-SOI; MIPS RISC-V aligns with mature FinFET. The goal is not ISA evangelism, but infrastructure—reducing friction between compute IP, tools, and manufacturing.

The Markets That Matter

High-end consumer AR/VR often benefits from leading-edge nodes, but it is economically narrow and consumer-driven. Robotics, by contrast, is a real-time systems problem where deterministic latency and power stability outweigh peak throughput. Automotive provides the clearest validation: long lifetimes, functional safety, and supply continuity dominate, and only a narrow slice of workloads truly require leading-edge silicon.

GlobalFoundries remains relevant because it aligned itself with the durable half of the electronics industry. While consumer and cloud compute dominate headlines, physical and infrastructure electronics reward capital discipline, stability, and long-term execution. GF exited the density arms race early and rebuilt around those realities. In an industry where many companies vanished by chasing scale they could not sustain, GlobalFoundries survived by choosing a different battlefield—and building a business model matched to its economics.

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The Chronicle of TSMC CoWoS

The Chronicle of TSMC CoWoS
by Daniel Nenni on 01-28-2026 at 10:00 am

Chronical of CoWoS

As semiconductor scaling slowed and system performance became increasingly constrained by data movement rather than raw compute, advanced packaging emerged as a decisive lever. Among these technologies, TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) represents a turning point in how high-performance systems are architected, manufactured, and scaled. Its evolution mirrors the industry’s shift from transistor-centric progress to system-level optimization.

At its core, CoWoS is a 2.5D integration technology. Logic dies and memory stacks are placed side by side on a silicon interposer, which is then mounted onto an organic substrate. The silicon interposer enables wiring densities far beyond what organic substrates can support, with metal line pitches in the low single-digit microns. Through-silicon vias pass signals and power vertically through the interposer, connecting it to the package substrate below.

The technical motivation for CoWoS was bandwidth density. Traditional off-package memory interfaces, such as DDR, rely on relatively long traces and limited I/O counts, resulting in high power consumption and latency. In contrast, CoWoS allows logic dies to interface with HBM stacks using thousands of parallel connections. Modern CoWoS implementations support memory bandwidth exceeding 3–5 TB/s per package, with energy efficiency measured in a few picojoules per bit, orders of magnitude better than conventional memory systems.

Early CoWoS deployments paired a single large logic die with two to four HBM stacks. Over time, the technology scaled aggressively. Interposer sizes expanded beyond 800–900 mm², pushing reticle and yield limits. Advanced packages now routinely integrate six to eight HBM stacks, each consisting of 8–12 DRAM dies bonded using TSVs and microbumps. Signal integrity across these short interposer traces allows operation at several gigabits per second per pin with minimal equalization overhead.

Manufacturing CoWoS is fundamentally different from traditional back-end packaging. Interposer fabrication resembles front-end wafer processing, using silicon wafers with multiple redistribution layers. TSV formation, wafer thinning, and precise die placement introduce yield sensitivities not seen in simpler packages. Assembly tolerances are tight: microbump pitches around 40 µm (and shrinking) require sub-micron alignment accuracy. Thermal management is equally critical, as large logic dies and dense memory stacks generate heat in close proximity.

As demand grew, CoWoS evolved beyond its original role as a memory enabler. The rise of chiplet-based architectures turned the interposer into a system fabric. Multiple logic dies, compute tiles, I/O dies, accelerators, could be interconnected with wide, low-latency links. This enabled designers to overcome reticle size limits while improving yield and design flexibility. CoWoS became a platform for heterogeneous integration rather than a single-purpose solution.

The AI acceleration boom of the 2020s elevated CoWoS from a niche capability to a strategic bottleneck. Training large neural networks requires massive parallel compute tightly coupled to enormous memory bandwidth. In many leading accelerators, performance scaling is limited less by transistor count than by HBM availability and interposer capacity. As a result, CoWoS production capacity became as strategically important as advanced logic nodes, with packaging throughput directly constraining system shipments.

Technically, CoWoS continues to push boundaries. Interposer routing layers have increased, power delivery networks have been reinforced to handle hundreds of watts per package, and mechanical designs have improved to manage warpage and stress. Variants have emerged to balance cost and performance, while coexistence with newer technologies such as hybrid bonding and 3D stacking is shaping next-generation systems.

Bottom Line: The chronicle of CoWoS is ultimately the story of how packaging became architecture. It demonstrated that performance, power efficiency, and scalability increasingly depend on microns of interconnect and millimeters of proximity. In an era where monolithic scaling alone can no longer carry progress, CoWoS stands as a defining example of how integration, not just miniaturization, drives the future of computing.

CONTACT TSMC

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TSMC’s CoWoS® Sustainability Drive: Turning Waste into Wealth

TSMC’s CoWoS® Sustainability Drive: Turning Waste into Wealth
by Daniel Nenni on 01-25-2026 at 12:00 pm

TSMC's CoWoS® Sustainability

In a significant example of how high-tech manufacturing can embrace environmental stewardship without compromising operational excellence, Taiwan Semiconductor Manufacturing Company has launched a sustainability initiative within its advanced packaging operations that both reduces waste and generates meaningful economic value. This drive, centered on TSMC’s CoWoS® (Chip on Wafer on Substrate) advanced packaging technology, demonstrates how innovation in recycling and circular practices can transform manufacturing byproducts into valuable resources resulting in annual green benefits of approximately NT$700+ million ($22M+ USD), alongside substantial carbon reduction.

At the heart of this sustainability effort is the repurposing of scrap or “waste” wafers, silicon discs produced and later deemed unsuitable during front-end production. Traditionally, such wafers are discarded once they fail to meet performance or quality specs. However, these silicon substrates still contain high-grade material and structural integrity valuable for secondary uses. Recognizing this, TSMC’s Materials Supply Chain Management Organization, in collaboration with its Advanced Packaging Technical Board and external suppliers, developed a specialized processing technology that turns scrap wafers into dummy dies, components essential in the CoWoS packaging process to maintain structural stability.

Dummy Dies and CoWoS®

To understand the significance of this initiative, one must appreciate the role of dummy dies in advanced semiconductor packaging. In CoWoS® technology, multiple active chips are stacked and integrated onto an interposer and substrate to create powerful multi-chip modules for high-performance computing, AI accelerators, and networking devices. During this process, dummy dies are inserted to fill space, balance mechanical stress, and maintain uniform thermal and electrical profiles. These are typically cut from brand-new wafers, which makes them a non-trivial fraction of packaging consumption—especially as demand for CoWoS® scales with burgeoning markets like AI, cloud computing, and advanced graphics.

Instead of using all new wafers to produce these dummy dies, TSMC’s cross-functional team developed a rigorous recycling methodology for scrap wafers. This involves selection, grinding, cleaning, and precision inspection to ensure recycled wafers meet the same strict quality requirements as newly sourced material. After processing, these recycled wafers are cut into dummy dies that are functionally and structurally suitable for CoWoS® assembly. This innovation not only salvages silicon that would otherwise go to waste, but also significantly shifts material sourcing dynamics toward sustainability.

Economic, Environmental, and Operational Impact

Early reports on the initiative’s outcomes have been compelling. As of late 2025, recycled wafers re-manufactured into dummy dies have been deployed across multiple advanced backend facilities, including Advanced Backend Fab 3, Fab 5, and Fab 6. The result is an estimated reduction of 10,205 metric tons of carbon emissions annually, underscoring a meaningful contribution toward TSMC’s broader climate goals. On the financial front, TSMC anticipates that this reuse of scrap wafers will generate a green benefit amounting to NT$746 million per year surpassing the NT$700 million mark cited in sustainability narratives.

This initiative exemplifies a practical circular economy model within semiconductor manufacturing: instead of viewing scrap material as waste to be disposed of at environmental cost, it becomes a resource to be refined and reintegrated into production. Beyond direct savings and emissions reductions, there are supply-chain ripple effects that encourage vendors and partners to invest in recycling technologies, improve material lifecycle tracking, and innovate in waste valorization.

TSMC’s approach aligns with its broader Environmental, Social, and Governance (ESG) strategy, which emphasizes resource circularity, energy efficiency, and environmental protection across its global operations. The company has consistently integrated sustainable practices—such as waste recycling programs and comprehensive environmental management—into its long-term operational blueprint.

Looking Forward

Looking ahead, TSMC plans to further expand the scope of recycled wafer use across different packaging technologies and processes, potentially including InFO (Integrated Fan-Out) packaging and beyond. By continually optimizing these techniques and extending collaboration across its supply chain, the company seeks to maximize resource efficiency while maintaining the highest product quality standards, a hallmark of its global leadership in semiconductor manufacturing.

Bottom line: TSMC’s CoWoS® sustainability drive encapsulates how bold environmental action and industrial innovation can work hand-in-hand, turning what was once waste into wealth economically and ecologically alike.

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Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing

Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing
by Daniel Nenni on 01-01-2026 at 10:00 am

Siemens Broadcom TSMC OIP2025 SemiWiki

Silent Data Corruption (SDC) represents a critical challenge in modern semiconductor design, particularly in high-performance computing environments like AI data centers. As highlighted in a collaborative presentation by Broadcom Inc. and Siemens EDA at the 2025 TSMC OIP event, SDC occurs when hardware defects cause erroneous computations without triggering detectable errors, leading to subtle yet devastating failures. In one customer experiment involving a 54-day training run on 16,384 GPUs, 419 unexpected interruptions were reported, with 6 attributed directly to SDC. Though rare, accounting for about 1.4% of fails, these incidents can disrupt mission-critical operations, such as AI model training, where reliability is paramount.

The presentation underscores the industry-wide nature of SDC, driven by shrinking process nodes and increasing chip complexity. Defects that evade manufacturing tests may manifest in-field due to aging, voltage fluctuations, or thermal stress. Traditional testing methods fall short here, as they require device removal for diagnostics, which is impractical in deployed systems. To combat this, the teams advocate for in-system testing capabilities that allow periodic checks without downtime. Running ATPG patterns directly in the field detects latent defects that could precipitate SDC, ensuring system integrity. For AI applications, this means integrating test suites that can be executed routinely, preventing costly interruptions. Moreover, new patterns tailored to SDC can be deployed remotely, extending device lifespan without physical intervention.

Siemens’ In-System Test (IST) solution emerges as a key enabler. Built on the Streaming Scan Network (SSN), IST interfaces with embedded deterministic test (EDT) structures to deliver ATPG patterns efficiently. The IST controller drives the SSN’s parallel interface, supporting high-bandwidth data transfer via protocols like APB or AXI. In Broadcom’s implementation, IST was adapted for an EDT-based design with a Streaming Scan Host at the chip level. The controller resides at the top level, loading patterns into local SRAM via an on-chip CPU. Block-level EDT patterns, originally for production testing, are retargeted to IST inputs, allowing selective testing of targeted blocks while maintaining functional operation elsewhere.

Implementation brought several design challenges to the fore. Functional isolation is paramount: “functional” blocks (e.g., CPU subsystems) must remain active to load and execute IST operations, while “targeted” blocks switch to scan mode for testing. This requires isolating scan inputs to prevent interference. All functional block inputs that could disrupt IST, such as interrupts or AXI signals, must be held in a “quiet” state. Outputs from targeted blocks, which toggle during capture, are gated to avoid propagating noise. Broadcom addressed this by inserting isolation blocks and enabling Test Data Registers for control.

Clock splitting posed another hurdle. Broadcom’s methodology places On-Chip Clock controllers (OCC) at the chip top due to custom clocking. Functional blocks need free-running clocks, but targeted ones require OCC activation for scan shifts. Solutions included branching pre-OCC clocks for functional paths or adding secondary OCCs for targeted branches, ensuring synchronized yet independent clock domains.

Verification and Static Timing Analysis added complexity. Typically, STA modes separate functional and Design-for-Test (DFT) paths, but IST demands a hybrid “merged” mode where some blocks are functional and others in DFT. The Siemens tool provides verification collaterals like transaction files, C code, and SystemVerilog tasks for Design Verification (DV) environments. Testing occurs on post-DFT netlists, incorporating boot sequences, which extends runtime. Close collaboration between DV and DFT teams was essential for deliverables and debugging handshakes.

Results from the APB-based IST implementation demonstrate feasibility. With a 32-bit wide subordinate interface and SSN data bus, hardware overhead was modest: the IST Controller (ISTC) added 200 flops and 5,000 normalized combinational logic units, while SSH contributed 1,000 flops and 30,000 units. Five intest modes were run for 2,500 patterns, using 2 MB on-chip SRAM (about 0.5 million 32-bit words). Pattern storage ranged from 165,000 to 260,000 words per mode, with counts of 22-35 patterns. Overall, ~1.9 million 32-bit words were managed, with 4 loads per mode, showcasing efficient compression and bandwidth utilization.

Bottom line: The collaboration between Broadcom and Siemens highlights IST’s role in mitigating SDC through in-field testing. Despite challenges in isolation, clocking, and verification, the solution was successfully implemented and verified in DFT and DV setups. Future efforts will extend to AXI-based IST, promising broader adoption. This approach not only enhances reliability in AI and hyperscale environments but also reduces field failures, underscoring the value of embedded deterministic testing in next-generation silicon.

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TSMC’s 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability Passion

TSMC’s 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability Passion
by Daniel Nenni on 01-01-2026 at 6:00 am

TSMC ESG Award Ceremony 2025

Taiwan Semiconductor Manufacturing Company has once again demonstrated its leadership in corporate sustainability with the successful conclusion of its 6th ESG AWARD, which attracted more than 5,800 proposals from employees across the organization. The overwhelming response reflects not only TSMC’s strong internal engagement but also the growing momentum of environmental, social, and governance (ESG) values within the global semiconductor industry.

Launched as a platform to encourage employee participation in sustainable innovation, the ESG AWARD has become one of TSMC’s most influential internal initiatives. The sixth edition recorded a significant increase in submissions compared to previous years, highlighting how sustainability has evolved from a corporate objective into a shared mission embraced by employees at all levels. Proposals covered a wide range of topics, including energy efficiency, carbon reduction, water resource management, waste minimization, supply chain responsibility, workplace well-being, and community engagement.

TSMC emphasized that the award is not merely a competition, but a catalyst for turning ideas into action. Many past award-winning proposals have been successfully implemented across fabs and offices, delivering measurable environmental and social benefits. These include innovations in energy-saving manufacturing processes, circular economy practices for materials reuse, and digital solutions to enhance operational transparency and governance. By empowering employees to contribute ideas directly linked to real-world impact, TSMC reinforces a culture where sustainability is embedded into daily operations.

The strong participation in the 6th ESG AWARD also reflects the broader pressures and responsibilities facing semiconductor manufacturers today. As demand for advanced chips grows alongside global digital transformation, the industry’s environmental footprint has come under increasing scrutiny. High energy consumption, water usage, and complex supply chains pose challenges that require both technological innovation and organizational commitment. TSMC’s approach demonstrates how internal engagement can play a crucial role in addressing these challenges proactively.

According to TSMC, proposals submitted this year showed greater maturity and cross-functional collaboration than in previous editions. Many teams combined technical expertise with ESG thinking, proposing solutions that balance productivity, cost efficiency, and sustainability. This shift suggests that ESG considerations are no longer treated as separate from core business goals, but rather as integral to long-term competitiveness and resilience.
The award process includes rigorous evaluation criteria, focusing on innovation, feasibility, scalability, and alignment with TSMC’s sustainability strategy. Selected proposals receive recognition and resources to support further development and implementation. This mechanism not only motivates employees but also accelerates the company’s progress toward its ESG targets, including net-zero ambitions and responsible supply chain management.

Beyond internal impact, the ESG AWARD sends a strong signal to stakeholders, including customers, investors, and partners. It highlights TSMC’s commitment to transparency, accountability, and continuous improvement in ESG performance. In an era where ESG metrics increasingly influence investment decisions and customer trust, such initiatives strengthen TSMC’s reputation as a responsible industry leader.

The enthusiasm generated by the 6th ESG AWARD underscores a key lesson for global corporations: sustainability thrives when employees are empowered to participate meaningfully.

Bottom Line: By transforming ESG from a top-down directive into a bottom-up movement, TSMC has ignited a passion that extends beyond awards and recognition. As the company looks ahead, the ideas and energy unleashed by this year’s record-breaking participation are expected to play a vital role in shaping a more sustainable future for both TSMC and the semiconductor industry as a whole.

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TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!

TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!
by Daniel Nenni on 12-31-2025 at 6:00 am

Synopsys Socionext 3d IC

Socionext’s recent run of rapid 3D-IC tape-outs is a noteworthy milestone for the industry with two successful tape-outs in just seven months for complex, multi-die designs aimed at AI and HPC workloads. That pace of iteration highlights how advanced packaging, richer EDA toolchains, and closer foundry-ecosystem collaboration are turning what used to be multi-year projects into achievable, repeatable engineering cycles.

At the heart of this acceleration are three interlocking trends: face-to-face 3D stacking that shrinks inter-die latency, process-node specialization across dies (e.g., TSMC N3 compute plus TSMC N5 I/O), and EDA/IP/cloud toolchains purpose-built for multi-die flows. Socionext’s taped-out designs reportedly combine an N3 compute die with an N5 I/O die using TSMC’s SoIC-X 3D stacking, a configuration that reduces interconnect distance and power while increasing bandwidth versus traditional 2D or 2.5D approaches.

Speeding a 3D-IC from concept to tape-out requires more than just clever floorplanning. Mechanical and thermal challenges (warpage, delamination, and heat removal), stringent reliability checks, and new timing/IR signoff flows make multi-die design complex. Socionext’s achievement illustrates how tightly integrated IP (PHYs, SerDes), 3D-aware design rules, and cloud-enabled EDA can remove bottlenecks: by automating design-rule checks for stacked interfaces, enabling distributed compute for large signoff runs, and providing pre-verified IP blocks that support high-speed interconnects. The company itself and partners emphasize that combining proven IP with AI-augmented EDA flows shortened development cycles and improved first-pass quality.

From a product perspective, 3D stacking supports an attractive value proposition for AI and HPC: put logic where it matters, optimize each die on the best process node for that function, and connect them with ultra-dense interfaces to reach system-level PPA (power, performance, area) that 2D designs cannot match. For vendors like Socionext — which target consumer SoCs as well as data-center accelerators — the ability to deliver working 3D-ICs rapidly opens new architectural options (heterogeneous dies, separable I/O fabrics, and modular chiplet ecosystems). Recent Socionext materials also show the company expanding 3DIC and 5.5D packaging support and promoting configurable chiplet building blocks to simplify system assembly.

Industry partnerships are central to this story. Socionext’s work with EDA and IP suppliers, and collaboration within the TSMC OIP ecosystem, demonstrate that 3D-IC success depends on an end-to-end supply chain: foundry stacking capabilities, packaging houses that can handle F2F and 5.5D substrates, EDA tools that understand multi-die timing and thermal behavior, and IP that is 3D-aware. The Synopsys writeup covering Socionext’s timeline explicitly credits the use of Synopsys’ 3D-enabled IP, AI-powered EDA flows, and cloud solutions as instrumental in hitting multiple tape-outs quickly.

What does this mean for the broader market? Faster, repeatable 3D tape-outs lower the barrier to entry for companies wanting to pursue heterogeneous integration. They also pressure incumbents to adopt modular approaches and to invest in multi-die verification and manufacturing readiness. However, scaling from tape-out to high-yield mass production remains the next big hurdle: yields, test strategies, and supply-chain throughput for advanced packaging will determine whether such rapid tape-out cycles translate into volume shipments and cost-effective products.

Bottom line: Socionext’s two tape-outs in seven months are more than a marketing sound bite, they’re a signal that the multi-die era is maturing. With the right mix of IP, EDA, foundry packaging, and ecosystem collaboration, complex 3D systems can move from experimental demos to production-grade devices on timelines that were hard to imagine just a few years ago.

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