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TSMC Expands Use of NVIDIA AI Technologies Across Chip Production Operations

TSMC Expands Use of NVIDIA AI Technologies Across Chip Production Operations
by Daniel Nenni on 06-03-2026 at 10:00 am
Categories: Foundries, TSMC

TSMC Expands Use of NVIDIA AI Technologies Across Chip Production Operations

TSMC, the world’s largest contract semiconductor manufacturer, is significantly expanding its deployment of NVIDIA artificial intelligence and accelerated computing technologies throughout its chip design and manufacturing operations. The initiative represents one of the most comprehensive applications of AI within advanced semiconductor fabrication, spanning lithography, process simulation, defect inspection, production scheduling, and factory optimization. The collaboration underscores how AI is becoming a critical enabler of next-generation semiconductor manufacturing as process technologies advance toward the angstrom era.

Modern semiconductor manufacturing has become extraordinarily complex, with advanced nodes requiring billions of transistors, hundreds of process steps, and nanometer-level precision. Traditional CPU-based computing environments often struggle to handle the computational demands associated with process development, computational lithography, and factory optimization. To address these challenges, TSMC is leveraging NVIDIA CUDA-X libraries, GPU-accelerated computing platforms, and AI models to accelerate critical workloads across the semiconductor production lifecycle.

One of the most significant areas of deployment is computational lithography. TSMC is utilizing NVIDIA cuLitho technology to accelerate the simulation and optimization processes required for advanced chip patterning. Computational lithography plays a vital role in translating circuit designs into physical patterns that can be printed onto silicon wafers. According to NVIDIA, TSMC has achieved improvements ranging from 20% to 50% in cycle time and cost effectiveness when using GPU-accelerated lithography workflows compared with conventional CPU-based approaches. These gains are particularly important as the industry moves toward increasingly sophisticated process technologies that require extensive optical proximity correction and mask optimization.

Beyond lithography, TSMC is applying AI and accelerated computing to transistor and process simulation. Semiconductor process development requires detailed modeling of materials, device structures, and manufacturing interactions. NVIDIA’s cuEST library enables significantly faster electronic structure and chemistry simulations, reportedly accelerating semiconductor material design calculations by as much as 50 times. Faster simulations allow engineers to evaluate more design alternatives, optimize materials, and reduce development cycles for future process nodes.

Factory operations are another major focus area. TSMC is deploying NVIDIA H200 GPU infrastructure and CUDA-based scheduling technologies to optimize production workflows and improve fab utilization. Semiconductor fabs generate enormous volumes of operational data, including equipment status, wafer movement, process parameters, and yield metrics. AI-powered scheduling and optimization systems can analyze these data streams in real time to improve throughput, reduce bottlenecks, and enhance overall manufacturing efficiency.

Quality control is also benefiting from AI integration. TSMC is using NVIDIA Metropolis and the NVIDIA TAO Toolkit to develop advanced vision AI systems for automated defect inspection. These systems are designed to detect nanometer-scale defects on wafers and photomasks with greater accuracy while reducing the need for repeated data labeling and model retraining. Automated inspection is increasingly important as feature sizes shrink and defect detection becomes more difficult using traditional methods. Improved defect identification directly contributes to higher yields and reduced manufacturing costs.

Another strategic initiative involves the development of digital twins for semiconductor manufacturing. TSMC and NVIDIA are collaborating on FabTwin, a virtual factory environment built using NVIDIA Omniverse technology. Digital twins enable engineers to simulate fab layouts, equipment configurations, material flows, and operational scenarios before implementing changes in physical production environments. Such capabilities help reduce deployment risks, improve resource planning, and accelerate process optimization across large-scale manufacturing facilities.

The expanded partnership reflects a broader industry shift toward AI-driven manufacturing. As advanced semiconductor nodes become more difficult and expensive to develop, AI is emerging as a critical tool for improving yield, reducing energy consumption, accelerating design cycles, and increasing fab productivity. NVIDIA CEO Jensen Huang stated that TSMC is bringing AI and accelerated computing directly into the fabrication environment to address some of the industry’s most complex design and manufacturing challenges. The result is a highly intelligent manufacturing ecosystem capable of supporting the next generation of AI processors, high-performance computing devices, and advanced semiconductor technologies.

Bottom line: TSMC’s adoption of NVIDIA AI technologies represents a significant milestone in the evolution toward autonomous, data-driven chip manufacturing. As AI workloads continue to grow globally, the integration of AI into semiconductor production itself may become a defining competitive advantage for leading foundries in the years ahead.

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TSMC Pioneers a New Era in AI-Powered Trade Secret Management, Achieving Intelligent Innovation

TSMC Pioneers a New Era in AI-Powered Trade Secret Management, Achieving Intelligent Innovation
by Daniel Nenni on 06-02-2026 at 6:00 am
Categories: AI, Foundries, TSMC

TSMC Pioneers a New Era in AI Powered Trade Secret Management
Launching a “Creativity Integration Partner Intelligent System” for Next-Level Efficiency

As semiconductor manufacturing becomes increasingly knowledge-intensive, protecting intellectual property and trade secrets has emerged as a strategic imperative. The world’s leading foundry, TSMC is advancing beyond conventional information security practices by integrating artificial intelligence into trade secret management. This transformation marks a significant milestone in the evolution of enterprise knowledge protection, enabling intelligent identification, classification, monitoring, and risk mitigation of critical proprietary information.

Trade secrets represent some of the most valuable assets within semiconductor organizations. Process technologies, design methodologies, equipment recipes, yield optimization techniques, materials research, and manufacturing know-how often provide competitive advantages worth billions of dollars. Traditional protection mechanisms, including access controls, document classification systems, and employee compliance programs, have become increasingly challenged by the sheer volume and complexity of digital information generated across advanced semiconductor operations.

TSMC’s AI-powered trade secret management framework addresses these challenges through the deployment of machine learning, natural language processing (NLP), and intelligent data analytics. Rather than relying solely on manual classification, AI systems continuously analyze documents, emails, technical reports, source code, process documentation, and collaborative communications to identify information that may constitute sensitive intellectual property.

A key component of this approach is semantic understanding. Modern large language models and domain-specific AI engines can recognize technical concepts, process parameters, device architectures, and manufacturing terminology associated with proprietary semiconductor technologies. This enables automated classification of sensitive content even when traditional keywords or predefined labels are absent. Such contextual awareness significantly improves the accuracy of trade secret identification while reducing administrative burden.

Another critical capability is intelligent risk detection. AI systems can monitor information flows across enterprise networks, cloud platforms, collaboration tools, and engineering databases to detect anomalous behavior. By establishing behavioral baselines, machine learning models can identify unusual access patterns, abnormal data transfers, excessive document downloads, or atypical collaboration activities that may indicate potential insider threats or unauthorized disclosure risks.

In advanced manufacturing environments, where thousands of engineers and researchers collaborate across multiple disciplines, real-time monitoring becomes essential. AI-driven analytics can evaluate risk scores dynamically, enabling security teams to prioritize investigations and respond proactively to emerging threats. This shift from reactive security management to predictive protection represents a fundamental advancement in enterprise risk management.

The integration of AI also enhances compliance and governance. Semiconductor companies operate within increasingly stringent regulatory environments that require comprehensive documentation of information security practices. AI-powered systems can automatically generate audit trails, maintain classification records, track data lineage, and provide evidence of policy enforcement. These capabilities improve transparency while supporting regulatory and legal requirements associated with trade secret protection.

From an operational perspective, intelligent trade secret management contributes to innovation acceleration. Engineers spend less time manually classifying documents and navigating security procedures, while organizations gain greater confidence in knowledge-sharing activities. AI enables a balance between collaboration and protection, ensuring that critical information remains secure without creating barriers to research and development productivity.

The emergence of generative AI introduces additional complexities and opportunities. As organizations increasingly deploy AI assistants and knowledge management platforms, protecting proprietary semiconductor data becomes even more important. TSMC’s approach demonstrates how AI can be leveraged not only as a productivity tool but also as a safeguard for intellectual capital. Advanced governance frameworks can ensure that sensitive information is appropriately managed within AI ecosystems while preventing inadvertent exposure through automated systems.

Looking ahead, AI-powered trade secret management is likely to become a standard capability across the semiconductor industry. As technology nodes advance toward increasingly sophisticated architectures and manufacturing processes, the value of proprietary knowledge will continue to grow. Organizations that successfully integrate AI into information protection strategies will be better positioned to safeguard innovation, maintain competitive differentiation, and support long-term technological leadership.

Bottom line: TSMC’s leadership in this area illustrates how artificial intelligence can transform cybersecurity and intellectual property management from administrative functions into strategic enablers of innovation. By combining advanced analytics, automation, and domain expertise, the company is establishing a new model for protecting the knowledge assets that drive the future of semiconductor technology.

Trade Secret Sustainable Intelligent Management Center

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Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P

Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2P
by Daniel Nenni on 06-01-2026 at 6:00 am
Categories: IP, Mixel, Silvaco, TSMC

Mixel MIPI 2026

The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability of C-PHY/D-PHY combo IP implemented on the TSMC N2P process, enabling higher bandwidth, lower power, and improved area efficiency for next-generation applications.

MIPI interfaces have become the de facto standard for connecting cameras, displays, and sensors in mobile and embedded systems. While D-PHY has long dominated the ecosystem, the increasing data requirements of advanced image sensors and ultra-high-resolution displays are accelerating adoption of MIPI C-PHY. The latest combo PHY solutions provide support for both standards within a unified implementation, giving SoC developers maximum flexibility while reducing integration complexity.

The Mixel combo IP is the industry’s first to support MIPI D-PHY v3.6 with Embedded Clock Mode (ECM), marking an important milestone in MIPI interface evolution. ECM eliminates the dedicated clock lane traditionally required in D-PHY architectures by embedding clock information within the data stream itself. This innovation reduces pin count, simplifies routing, and improves channel efficiency while maintaining backward compatibility with existing MIPI ecosystems.

For advanced nodes such as TSMC N2P, these architectural improvements are particularly significant. The N2P process provides enhanced performance-per-watt characteristics compared to prior generations, making it well suited for power-sensitive applications that still require extremely high throughput. Combining N2P with a next-generation combo PHY allows designers to fully leverage the node’s capabilities while minimizing system-level overhead.

The integration of C-PHY and D-PHY functionality into a single IP block also enables seamless interoperability across multiple use cases. Camera subsystems, for example, may require D-PHY compatibility for legacy sensors while simultaneously supporting high-bandwidth C-PHY links for next-generation image processing pipelines. A combo implementation reduces die area compared to separate PHY solutions and simplifies validation across different product configurations.

MIPI C-PHY delivers substantially higher throughput efficiency than conventional D-PHY implementations by utilizing three-wire trios and embedded clocking techniques. This enables higher effective bandwidth without proportionally increasing pin count or operating frequency. As image sensor resolutions continue to scale beyond 100 megapixels and display refresh rates move toward 240Hz and beyond, these efficiency gains become increasingly valuable.

Meanwhile, D-PHY v3.6 introduces Embedded Clock Mode specifically to address scaling challenges associated with traditional source-synchronous clock architectures. By embedding the clock within the transmitted data stream, ECM reduces EMI concerns and improves signal integrity in dense package environments. This is especially beneficial in advanced packaging technologies such as chiplets and fan-out integration, where routing congestion and signal coupling are major design considerations.

The implementation of combo PHY IP on TSMC N2P also requires extensive analog and mixed-signal optimization. Advanced process nodes introduce new variability and tighter voltage margins, making robust PHY design more challenging. High-speed I/O circuits must maintain signal integrity across process, voltage, and temperature corners while meeting increasingly stringent power budgets.

To address these requirements, modern combo PHY architectures incorporate adaptive equalization, low-jitter PLLs, advanced calibration techniques, and sophisticated power management schemes. These features ensure reliable operation at multi-gigabit data rates while minimizing active and standby power consumption. For battery-powered devices, these optimizations directly translate into improved user experience and extended operating life.

Another important advantage of N2P-based PHY implementations is support for AI-enabled edge systems. Emerging applications such as autonomous robotics, intelligent surveillance, and spatial computing require massive sensor bandwidth combined with low latency and high energy efficiency. MIPI interfaces are increasingly central to these workloads because they provide standardized, scalable connectivity between sensors and compute engines.

Automotive applications are also driving demand for advanced PHY solutions. Next-generation vehicles integrate multiple high-resolution cameras, driver monitoring systems, and immersive displays, all of which require robust high-speed interfaces. Combo PHY implementations supporting both C-PHY and D-PHY enable automotive SoCs to accommodate a broad range of sensor and display configurations while maintaining compliance with evolving industry standards.

Bottom line: As semiconductor scaling continues, interface IP is becoming a critical differentiator for SoC platforms. The availability of C-PHY/D-PHY combo IP on TSMC N2P demonstrates how interface technologies are evolving alongside process innovation to meet escalating bandwidth and efficiency demands. With support for MIPI D-PHY v3.6 Embedded Clock Mode, Mixel’s implementation represents a significant advancement in next-generation connectivity infrastructure for mobile, automotive, AI, and consumer electronics applications.

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TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade

TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade
by Daniel Nenni on 05-25-2026 at 10:00 am
Categories: Foundries, TSMC

TSMC’s Lithium Iron Battery Generation Upgrade Project

As semiconductor manufacturing becomes increasingly dependent on uninterrupted power and energy efficiency, battery reliability has emerged as a critical operational issue for advanced fabs. Taiwan Semiconductor Manufacturing Company, better known as TSMC, is addressing this challenge through an ambitious global initiative called the “Lithium Iron Battery Generation Upgrade Project.” The program represents one of the semiconductor industry’s most comprehensive battery modernization efforts, covering approximately 408,000 lithium iron phosphate batteries installed across the company’s domestic and international fabrication facilities.

The project is designed to improve both operational resilience and environmental safety. TSMC has been gradually replacing traditional lead-acid batteries in uninterruptible power supply systems with lithium iron batteries because of their higher efficiency, longer lifecycle, and lower environmental impact. The transition also supports the company’s broader sustainability goals, including reduced electricity consumption and lower carbon emissions. Earlier initiatives using LFP batteries reportedly enabled annual electricity savings of approximately 17.1 million kilowatt-hours.

TSMC’s battery upgrade journey has unfolded in several stages. The company first introduced first-generation lithium iron batteries in 2017 after conducting extensive in-fab production verification. These systems primarily monitored battery voltage through sampling boards to maintain safe operation. In 2018, TSMC adopted second-generation systems in response to the International Electrotechnical Commission’s IEC 62619 safety standards for industrial lithium battery applications. The upgraded Battery Management System (BMS) added monitoring capabilities for temperature, state of charge, and battery health, enabling improved operational oversight.

The real transformation began in 2019 when TSMC started developing third-generation lithium iron battery systems with suppliers and technical experts. These new systems significantly expanded monitoring functionality by adding real-time current tracking and integrating directly with the fab’s Supervisory Control and Data Acquisition infrastructure. Through this integration, battery data can be transmitted continuously to centralized monitoring platforms for remote diagnostics and predictive analysis.

The third-generation BMS can precisely monitor critical battery parameters, including voltage, current, temperature, state of charge, and state of health. According to TSMC, the system can immediately identify abnormal operating conditions and pinpoint fault locations, improving emergency response efficiency by approximately 25 percent. In high-volume semiconductor manufacturing environments, where even a brief power disruption can affect wafer production worth millions of dollars, this level of visibility and rapid response capability is especially important.

Safety validation has become another cornerstone of the project. In 2024, TSMC conducted thermal runaway experiments on lithium iron batteries to evaluate battery behavior under extreme conditions and verify the effectiveness of BMS protection mechanisms. Thermal runaway is one of the primary safety concerns associated with large-scale battery systems because overheating in a single cell can potentially trigger cascading failures. By performing controlled testing, TSMC aimed to confirm that its upgraded systems could prevent hazardous events and maintain stable operations in demanding industrial settings.

By the first quarter of 2026, TSMC had fully upgraded all first- and second-generation lithium iron battery management systems to the third-generation standard across its facilities. The company is also deploying an additional layer of protection through lithium iron battery breaker interlocking trip devices. These devices are designed to automatically disconnect power when the BMS detects abnormalities, minimizing the risk of equipment damage or fire-related incidents. Installation of the trip devices is expected to be completed by 2027.

The significance of the project extends beyond battery management. Semiconductor fabs are among the world’s most energy-intensive manufacturing environments, and ensuring reliable power infrastructure is increasingly important as AI-related chip production expands globally. TSMC’s investment in advanced UPS battery systems aligns with its larger environmental and operational strategy, including commitments to renewable energy adoption and sustainable manufacturing practices.

The “Lithium Iron Battery Generation Upgrade Project” illustrates how advanced manufacturing companies are beginning to treat energy storage systems not merely as backup infrastructure, but as intelligent, networked safety platforms. By combining advanced battery chemistry, real-time analytics, SCADA integration, and automated protection mechanisms, TSMC is setting a new benchmark for operational safety and energy resilience in semiconductor manufacturing. As fabs become larger, more automated, and increasingly dependent on uninterrupted power, projects like this may become standard practice across the global semiconductor industry.

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ASML High-NA EUV is Not Ready for High-Volume Production

ASML High-NA EUV is Not Ready for High-Volume Production
by Daniel Nenni on 05-22-2026 at 8:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, TSMC
16 Comments

ASML Elephant High NA EUV

Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just a technical decision. It is now a value proposition decision.

As things stand today, the answer appears to be no: the benefits of High-NA EUV do not justify the cost and risk at 1.4nm.

One of the biggest industry shifts is that foundry customers now have a voice in process technology decisions, and you can thank TSMC for that. TSMC’s collaborative business model gives major customers direct input on manufacturing roadmaps. The top TSMC customers I have spoken with are not ready to embrace High-NA EUV given the current economics and manufacturing risks.

TSMC has said as much publicly during the last two Technology Symposiums. In briefings at both the 2025 Symposium and last month’s event, Dr. Kevin Zhang, Senior Vice President and Deputy Co-COO, made it clear that High-NA EUV is simply too expensive relative to the expected benefit.

Intel had planned to introduce High-NA EUV at the 14A node under former CEO Pat Gelsinger. That was a classic IDM-style decision made largely without customer feedback. Under Lip-Bu Tan, however, customers are expected to have far greater influence over technology choices—which likely means Intel will move closer to the TSMC customer-first model. Samsung may not have much choice either. Foundry customers have spoken.

To be clear, ASML’s High-NA EUV technology works. The question is not technical feasibility. The real question is whether it can achieve the yield, uptime, and economics required for profitable high-volume manufacturing.

The core technical challenge is that High-NA EUV dramatically reduces process margins. Standard EUV tools operate at a numerical aperture (NA) of 0.33, while High-NA increases this to 0.55. The higher NA improves resolution and enables smaller transistor features, but it also significantly reduces depth of focus. In practical terms, wafers must remain almost perfectly flat during exposure. Even tiny variations in wafer topography, thermal distortion, or vibration can create pattern defects that reduce yield.

Photoresists are another major obstacle. High-NA systems require thinner resist films because thicker films exceed the narrow focus window. However, thinner resists absorb fewer EUV photons, increasing stochastic defects such as broken lines, missing holes, and edge roughness. These defects occur randomly and are extremely difficult to eliminate through standard process optimization. At advanced nodes, even a very small number of stochastic defects can make chips unusable.

EUV also faces a fundamental photon problem. Unlike deep ultraviolet lithography, EUV operates with relatively low photon counts. At High-NA dimensions, statistical fluctuations in photon absorption become significant enough to impact pattern fidelity. Electron blur following photon absorption further reduces precision. As the industry approaches the angstrom era, these random physical effects become increasingly difficult to control.

Mask technology introduces another layer of complexity. High-NA EUV uses anamorphic optics, meaning image scaling differs between horizontal and vertical directions. This requires entirely new mask architectures and correction algorithms. EUV masks are already among the most complex manufactured objects in the semiconductor industry, and High-NA masks push defect tolerances even further. Some defects are only visible under EUV illumination, making inspection extraordinarily difficult.

Pellicles remain another unresolved issue. These thin protective membranes shield masks from contamination, but High-NA systems require much higher source power levels, creating severe thermal stress. Existing pellicle materials can warp or degrade under sustained exposure. New materials are under development, but they are not yet fully qualified for continuous high-volume manufacturing.

Throughput and uptime are equally critical. Semiconductor fabs depend on extremely high utilization rates because downtime directly impacts profitability. High-NA tools are still early-generation systems and have not demonstrated the long-term reliability of mature EUV platforms. Even relatively small interruptions can create major economic consequences in leading-edge fabs operating 24/7.

Cost may ultimately be the largest barrier of all. Each High-NA EUV scanner costs approximately $350 million to $400 million, making it the most expensive manufacturing tool ever built. Beyond the scanner itself, fabs require major infrastructure upgrades involving power delivery, cooling, vibration isolation, and cleanroom redesign. The total investment required for High-NA production is enormous, and foundries must determine whether the incremental scaling benefits justify the expense.

TSMC appears to have already made that calculation. Rather than rushing into High-NA deployment, the company is extending existing 0.33 NA EUV systems through multipatterning and process optimization. That decision reflects concerns not only about technical maturity, but also about economic return.

The broader ecosystem is another issue. Lithography does not operate in isolation. Etch, deposition, metrology, inspection, design software, packaging, and yield-learning infrastructure must all evolve together. High-NA EUV introduces new interactions throughout the manufacturing flow, meaning the entire semiconductor ecosystem must mature before stable high-volume yields become realistic.

Bottom line: High-NA EUV is stuck in the difficult transition between laboratory success and industrial maturity. The technology has clearly demonstrated capability in research environments and pilot production, but successful semiconductor manufacturing requires much more than technical proof points. Yield stability, uptime, defect reduction, ecosystem readiness, infrastructure investment, and economic viability must all improve before High-NA EUV can become mainstream production technology.

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Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC

Siemens EDA Expands AI and Advanced Packaging Collaboration with TSMC
by Daniel Nenni on 05-20-2026 at 10:00 am
Categories: 3D IC, Chiplet, EDA, Events, Foundries, Siemens EDA, TSMC

SIemens EDA TSMC Teshnical Symposium 2026

At the recent TSMC Technology Symposium 2026, Siemens EDA reinforced its position as one of the key ecosystem partners supporting TSMC in the race toward AI-driven semiconductor design, advanced packaging, and next-generation process technologies. The annual forum has become one of the semiconductor industry’s most important gatherings, bringing together foundry customers, EDA suppliers, IP vendors, and packaging innovators to align around future technology nodes and design methodologies.

A major theme throughout the event was the growing impact of artificial intelligence on chip development. Siemens EDA used the symposium to highlight expanded collaboration with TSMC focused on AI-powered automation across the semiconductor workflow. The companies announced joint work involving automated Design Rule Check fixing, AI-assisted physical verification, and intelligent design optimization using Siemens’ recently introduced Fuse EDA AI System.

The partnership reflects a broader industry shift. Semiconductor complexity is increasing dramatically as AI accelerators, high-performance computing devices, automotive processors, and chiplet-based architectures push beyond the limits of traditional design methods. Designers are now managing multi-die systems, advanced 3D packaging, massive data throughput requirements, and power delivery challenges simultaneously. As a result, AI-enabled EDA tools are becoming critical to reducing development cycles and improving productivity.

Siemens emphasized that its AI technologies are being integrated directly into production-proven tools such as Calibre and Aprisa. According to the company, TSMC is collaborating with Siemens to improve multi-step automation for DRC-centric physical verification while also helping engineers gain faster access to design insights and guided recommendations during implementation.

One of the most significant aspects of the announcement involved support for TSMC’s latest process technologies. Siemens reported certifications for its EDA tools on multiple advanced nodes including N3A, N3C, N2P, A16, and A14 technologies. These certifications are essential because semiconductor companies require validated design flows before committing billions of dollars to advanced-node tape-outs. By securing early enablement and certification, Siemens ensures that mutual customers can begin development with confidence on TSMC’s newest manufacturing platforms.

Another important focus at the forum was advanced packaging and 3D integration. TSMC continues expanding its 3DFabric and CoWoS packaging ecosystems to support increasingly complex AI systems. Siemens highlighted capabilities within its Calibre 3DStack platform that address interface checking, connectivity verification, inter-chiplet DRC validation, antenna analysis, and current density analysis for 3D systems. These capabilities are particularly important as AI processors move toward heterogeneous integration involving logic, memory, photonics, and specialized accelerators inside a single package.

Industry analysts noted that the symposium showcased an increasingly competitive environment among the three leading EDA vendors: Siemens, Synopsys, and Cadence. While all three announced expanded TSMC collaborations, Siemens differentiated itself through its emphasis on agentic AI orchestration and design-to-manufacturing integration. The company’s strategy appears centered on automating complex workflows that traditionally require extensive engineering intervention.

The timing of these announcements is significant. TSMC’s roadmap now includes multiple sub-2nm technologies, backside power delivery, advanced automotive nodes, and co-packaged optics initiatives. Each of these innovations introduces new design and verification challenges. Semiconductor companies are under intense pressure to reduce design turnaround time while maintaining power, performance, and reliability targets. AI-assisted automation is increasingly viewed as the only viable way to sustain productivity improvements at advanced nodes.

At the symposium, TSMC also reinforced the importance of its Open Innovation Platform (OIP) ecosystem, where Siemens remains a key partner. The OIP model enables close collaboration between foundry technologies and EDA tool providers, ensuring early process enablement and optimized design flows. Siemens’ long-standing participation in this ecosystem has allowed it to remain deeply integrated into TSMC’s technology roadmap.

The broader semiconductor industry context also shaped discussions at the event. According to industry commentary surrounding the symposium, AI demand is driving unprecedented semiconductor growth, especially in high-performance computing infrastructure. Advanced packaging capacity, power delivery innovation, and chiplet architectures are becoming central to competitive differentiation. As these challenges intensify, EDA vendors are evolving from traditional software providers into strategic enablers of AI-era semiconductor development.

For Siemens EDA, the TSMC Technical Forum served as more than a technology showcase. It was a strategic statement about the future direction of chip design. The company is positioning itself at the intersection of AI automation, advanced manufacturing enablement, and heterogeneous system integration. By strengthening collaboration with TSMC, Siemens aims to help semiconductor companies accelerate innovation while managing the escalating complexity of next-generation designs.

Bottom line: As AI continues reshaping the semiconductor industry, partnerships like Siemens and TSMC will likely become even more important. Future chip development will depend not only on transistor scaling, but also on intelligent automation, advanced packaging methodologies, and tightly integrated ecosystem collaboration. The announcements made at the TSMC Technical Forum suggest that Siemens EDA intends to play a central role in enabling that future.

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imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling
by Daniel Nenni on 05-19-2026 at 6:00 am
Categories: 3D IC, Chiplet, Foundries, TSMC

TSMC 3DFabric Alliance Expansion Signals New Era of System Level Scaling

imec announced that IC-Link by imec has joined the TSMC 3DFabric Alliance, a strategically important move that reflects the semiconductor industry’s transition from traditional monolithic scaling toward heterogeneous integration, chiplet architectures, and advanced packaging-driven system optimization. The partnership is technically significant because it combines imec’s globally respected research expertise in advanced packaging and system scaling with TSMC’s production-leading 2.5D and 3D integration ecosystem, enabling faster commercialization of next-generation AI, HPC, automotive, and mobile semiconductor solutions.

For decades, semiconductor innovation was driven primarily by transistor scaling under Moore’s Law. Smaller transistors delivered higher performance, lower power, and lower cost per function. However, as process technologies approach physical and economic scaling limits below 3nm, system-level innovation has become equally important. Today, the bottleneck in many AI and HPC systems is no longer only compute density, but memory bandwidth, interconnect latency, thermal management, and power delivery. Advanced packaging technologies such as chiplets, 2.5D interposers, wafer-level integration, and 3D die stacking are increasingly becoming the primary mechanism for improving overall system performance.

TSMC’s 3DFabric platform addresses these challenges through a portfolio of advanced integration technologies that includes TSMC-SoIC®, CoWoS®, InFO, and TSMC-SoW™. These technologies enable heterogeneous integration, allowing logic, memory, analog, photonics, and specialized accelerators to be integrated into a unified package. Instead of building one extremely large monolithic die, designers can partition functionality across multiple optimized chiplets fabricated on different process nodes and interconnected with ultra-high bandwidth packaging technologies. This approach improves yield, reduces development cost, accelerates design reuse, and enables greater scalability for AI infrastructure.

The addition of IC-Link to the 3DFabric Alliance is important because IC-Link functions as a bridge between semiconductor research and industrial manufacturing. Imec already possesses deep expertise in heterogeneous integration, silicon photonics, advanced packaging, and ASIC development. Through IC-Link, these research capabilities can now be directly connected to TSMC’s production ecosystem. This reduces the traditional gap between R&D innovation and manufacturable commercial products.

One of the most critical technical implications is co-optimization between silicon design and packaging. In advanced AI systems, packaging is no longer treated as a backend assembly step. Instead, package architecture must be designed simultaneously with silicon architecture. Thermal dissipation, power delivery networks, interconnect topology, and memory placement all influence final system performance. The 3DFabric Alliance enables ecosystem participants to collaborate earlier in the design cycle, which improves design convergence and shortens time-to-market for complex multi-die systems.

This collaboration is particularly relevant for AI and HPC applications. Large language models and AI inference engines require enormous memory bandwidth and low-latency interconnects between compute and memory resources. Traditional package architectures cannot efficiently support these requirements. Technologies like CoWoS and SoIC enable high-density die-to-die interconnects and vertically stacked memory integration, significantly increasing bandwidth while reducing power consumption per bit transferred. This packaging-centric architecture is now central to competitive AI accelerator design.

Another major technical advantage is access to advanced manufacturing readiness. Through the alliance, IC-Link customers gain earlier access to TSMC’s advanced packaging flows and validated ecosystem infrastructure. This includes design enablement, IP integration, packaging qualification, substrate technologies, and manufacturing interoperability. For fabless semiconductor companies, especially startups and European innovators, this reduces development risk and accelerates the path from prototype to high-volume production.

The announcement also reflects the growing importance of Europe in advanced semiconductor development. Europe has historically been strong in semiconductor equipment, automotive electronics, and research, but less dominant in leading-edge manufacturing ecosystems. Imec has emerged as one of the world’s most influential semiconductor R&D organizations, and this partnership strengthens Europe’s role in advanced packaging innovation. By integrating with TSMC’s global ecosystem, imec can help European companies access state-of-the-art 3D IC technologies without building independent manufacturing infrastructure from scratch.

From a system architecture perspective, the industry is rapidly moving toward modular semiconductor design. Chiplet-based systems allow designers to independently optimize compute, I/O, memory, RF, and photonics functions using different process technologies. This modularity improves flexibility and lowers development cost while enabling rapid innovation cycles. However, chiplet integration introduces major complexity in interconnect density, signal integrity, thermal coupling, and package reliability. Ecosystem collaboration therefore becomes essential. The 3DFabric Alliance was specifically created to solve these integration challenges through cross-industry collaboration between foundries, packaging providers, EDA vendors, IP suppliers, and manufacturing partners.

The timing of the announcement is also important. Demand for advanced packaging capacity has surged because of AI infrastructure growth. Packaging technologies such as CoWoS have become strategic industry bottlenecks. Semiconductor companies increasingly compete not only on transistor technology, but on the ability to integrate large-scale AI systems efficiently. By joining the alliance now, IC-Link positions itself to support the next wave of AI accelerator development and heterogeneous system integration.

Bottom line: IC-Link joining the TSMC 3DFabric Alliance represents more than a business partnership. It signals a broader industry transformation in which advanced packaging and 3D integration are becoming primary drivers of semiconductor innovation. The collaboration combines imec’s research leadership with TSMC’s manufacturing scale to accelerate the development of complex multi-die systems optimized for AI, HPC, automotive, and next-generation communications. As semiconductor scaling becomes increasingly system-centric, alliances like this will define the future competitive landscape of the semiconductor industry.

Also Read:

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. Y.J. Mii on TSMC Technology Leadership in 2026

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

 

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TSMC’s Record Tool Orders Hint at Another CapEx Shockwave

TSMC’s Record Tool Orders Hint at Another CapEx Shockwave
by Daniel Nenni on 05-15-2026 at 8:00 am
Categories: Foundries, TSMC

TSMC’s Record Tool Orders Hint at Another CapEx Shockwave 2026

TSMC’s latest Board of Directors capital appropriation announcement may appear mixed on the surface, but a closer look reveals one important conclusion: The company is quietly setting the stage for another potential upward revision to its already aggressive 2026 capital expenditure outlook. The headline figure of $31.3B in newly approved capital appropriations was below the massive $45.0B approved in the prior quarter, yet the composition of this spending tells a much more constructive story for the semiconductor equipment ecosystem.

The most notable development is the continued acceleration in Advanced Node equipment investment. TSMC approved approximately $21.0B of Advanced Node-related equipment spending this quarter, representing the highest quarterly authorization level since we began tracking the company’s BoD capital approvals in 4Q19. Even though total approved spending declined sequentially, the shift toward leading-edge wafer fabrication equipment indicates that TSMC’s strategic focus remains firmly centered on expanding advanced logic capacity.

This distinction matters. Infrastructure spending and specialty technology investments can fluctuate depending on timing, construction schedules, or packaging initiatives. Advanced Node equipment approvals, however, are a far cleaner signal of future semiconductor manufacturing activity. They directly correlate with purchases of lithography, process control, deposition, etch, and metrology systems required for ramping leading-edge nodes such as N2 and A16.

At the same time, there was a notable absence of new approvals for Specialty Devices and Advanced Packaging. Last quarter’s record approval in this category was later understood to be tied to silicon photonics, CoWoS, and SoIC-related investments. The lack of follow-on approvals this quarter should not necessarily be interpreted as weakening demand. Rather, it likely reflects the exceptionally large allocation already approved previously. Given the long lead times and substantial scale of advanced packaging infrastructure deployment, TSMC may simply be digesting prior commitments before authorizing another major tranche of spending.

Infrastructure spending also normalized this quarter. The $10.3B approval level was meaningfully lower than the record $21.4B authorized in the prior quarter. However, this moderation appears more cyclical than structural. Infrastructure allocations often fluctuate depending on the timing of fab shell construction, utility expansion, overseas manufacturing projects, and regional government incentives. The key takeaway is that infrastructure moderation did not come alongside any slowdown in Advanced Node investment intensity.

Perhaps the most important data point from this quarter is the emerging disconnect between approved future spending and TSMC’s current annual CapEx guidance. Assuming BoD capital appropriations generally represent roughly the next 12 months of spending activity, the trailing twelve-month Advanced Node equipment authorization level has now climbed to approximately $55.0B. That figure alone nearly matches TSMC’s entire current 2026 capital expenditure guidance of roughly $56B.

This creates an increasingly difficult mathematical setup. If Advanced Node equipment alone already represents nearly the full-year CapEx plan, then either spending cadence must slow materially in coming quarters or total CapEx guidance will need to move higher. Given current AI infrastructure demand trends, slowing investment appears unlikely.

The broader industry backdrop strongly supports the latter scenario. AI-driven compute demand continues to accelerate across hyperscale data centers, sovereign AI projects, enterprise deployments, and edge inference applications. Leading-edge silicon demand remains supply constrained, particularly for advanced GPUs, AI accelerators, networking ASICs, and high-bandwidth memory integration. TSMC remains the dominant manufacturing partner for virtually all major AI chip developers, placing extraordinary pressure on its advanced manufacturing capacity roadmap.

As a result, TSMC’s quarterly CapEx run rate likely needs to increase further over the next twelve months. The company’s N2 ramp, advanced packaging expansion, overseas fab deployment, and ongoing EUV intensity growth all point toward sustained elevated investment levels. This is why the probability of a 2026 CapEx raise at TSMC’s 2Q26 earnings conference call in July appears to be increasing.

Bottom line: The latest TSMC approval data reinforces a critical industry theme: despite periodic fluctuations in quarterly headline numbers, leading-edge semiconductor investment remains in a structural expansion phase. AI demand is fundamentally altering semiconductor infrastructure requirements, and TSMC’s capital allocation patterns continue to reflect that reality. In fact, the latest BoD approvals may ultimately be remembered less for the sequential decline in total authorizations and more as an early signal that TSMC’s current 2026 CapEx framework is already becoming too conservative.

Also Read:

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. Y.J. Mii on TSMC Technology Leadership in 2026

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

Dr. Cliff Hou and the TSMC N2 Process Technology

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Synopsys and TSMC Deepen AI Design Alliance: What It Means

Synopsys and TSMC Deepen AI Design Alliance: What It Means
by Kalar Rajendiran on 05-05-2026 at 10:00 am
Categories: 3D IC, AI, Chiplet, EDA, IP, Photonics, Synopsys, TSMC

Synopsys Powering the next generation of AI

A recent announcement from Synopsys signals a meaningful escalation in the race to build next-generation AI hardware. The expanded collaboration between Synopsys and TSMC brings together silicon-proven IP, AI-driven design tools, and cutting-edge manufacturing processes in a tightly integrated effort to accelerate high-performance computing (HPC) and AI system development. More than a routine partnership update, the move reflects a broader industry transition toward ecosystem-level innovation, where success depends on how well design, IP, and fabrication technologies align from the outset.

What Was Announced

At the core of the announcement is a three-part expansion of capabilities spanning IP, design flows, and system-level enablement.

Synopsys is advancing silicon-proven interface IP validated on TSMC’s most advanced nodes, including 3nm and emerging 2nm-class processes. These include next-generation standards such as M-PHY v6.0 which is now achieving industry-first low-power silicon bring-up on N2P, alongside tapeouts of 64G UCIe IP and 224G high-speed interconnect IP. Together, these technologies form the backbone of AI chips that must move massive volumes of data with minimal latency and power overhead, particularly in bandwidth-constrained environments.

The companies are also extending certified electronic design automation (EDA) flows with a sharper emphasis on increasingly agentic AI-driven optimization. Collaboration on run assistance within Synopsys Fusion Compiler, leveraging TSMC’s A14 process and NanoFlex Pro architecture, is aimed at improving power, performance, and area (PPA) while boosting design productivity. This signals a shift from passive AI assistance toward more active, decision-guiding systems that can materially impact how chips are designed at advanced nodes.

Beyond individual dies, the partnership continues to push into advanced packaging and system-level integration. Synopsys’ 3DIC Compiler platform is now enabling productivity improvements for TSMC’s CoWoS technology at interposer sizes reaching up to 5.5 times the reticle limit, underscoring the scale of modern multi-die designs. This is complemented by multiphysics simulation capabilities that address thermal, electrical, and optical interactions. These requirements are becoming essential as chips evolve into tightly integrated systems.

The announcement also highlights expansion into new application domains. In automotive, Synopsys is offering a UCIe IP solution compliant with ASIL B functional safety requirements on TSMC’s N5A process, marking a significant step toward enabling chiplet-based architectures in safety-critical environments. Meanwhile, advancements in M-PHY IP are targeted at next-generation mobile and storage applications, including smartphones that demand both high performance and power efficiency.

Finally, the collaboration advances AI infrastructure through co-packaged optics. Multiphysics design enablement for co-packaged optical systems, including TSMC’s COUPE design flow, spans optical path simulation, electromagnetic extraction, and system-level analysis, and is paired with 224G IP designed to support optical Ethernet and emerging interconnect standards such as UALink. Together, these capabilities directly address the growing bandwidth and energy challenges facing large-scale AI systems.

Why This Matters for AI Hardware

The significance of this partnership lies in how it tackles the core constraints of modern AI workloads. As compute performance scales, the bottlenecks have shifted toward data movement, power efficiency, and system integration. By combining high-speed IP, agentic AI-driven design tools, and advanced packaging technologies, Synopsys and TSMC are reducing the gap between design complexity and manufacturable silicon.

The introduction of agentic run assistance in EDA tools marks a particularly important inflection point. Rather than simply accelerating existing workflows, these capabilities begin to reshape them, enabling engineers to delegate increasingly complex optimization tasks to AI systems. This has the potential to significantly compress development cycles while improving overall design quality.

Equally critical is the focus on bandwidth. Technologies such as 224G interconnects and co-packaged optics are emerging as key enablers for scaling AI infrastructure, where moving data efficiently is often more challenging than processing it. By integrating these capabilities into both IP and design flows, the partnership addresses one of the most pressing limitations in next-generation AI systems.

The expansion into automotive and mobile markets further underscores the breadth of this strategy. It signals that advanced-node, multi-die, and chiplet-based designs are no longer confined to hyperscale data centers but are beginning to permeate safety-critical and consumer applications as well.

Market And Industry Implications

The expanded alliance reinforces Synopsys’s position as a central player in AI silicon enablement while strengthening TSMC’s ecosystem around its most advanced process nodes. For chip designers, tighter integration between EDA tools and foundry technologies can translate into faster time-to-market and reduced development risk, particularly when targeting cutting-edge nodes.

At the same time, the partnership reflects a broader industry dynamic in which design tools and manufacturing processes are becoming increasingly interdependent. As flows become more deeply optimized and certified for specific nodes, the cost and complexity of switching ecosystems rise. This creates a form of strategic lock-in that benefits tightly aligned partners while raising barriers for competitors.

The Bigger Picture

Taken together, the announcement illustrates a shift in how semiconductor innovation is defined in the AI era. Progress is no longer driven solely by transistor scaling but by the ability to coordinate across multiple layers of the technology stack, from design software and reusable IP to packaging and system integration.

The Synopsys–TSMC collaboration points to a future where chips are conceived not as isolated components but as parts of larger, highly integrated systems spanning data centers, vehicles, and mobile devices. In this landscape, competitive advantage will increasingly depend on how effectively companies can bring together tools, technologies, and partners to deliver complete, optimized solutions.

As AI continues to push the limits of performance and complexity, partnerships like this are likely to define the pace of innovation. The companies that succeed will be those that can bridge the gap between design intent and real-world deployment, turning increasingly sophisticated ideas into scalable, manufacturable systems.

You can access the entire press announcement here.

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Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions
by Daniel Nenni on 05-01-2026 at 6:00 am
Categories: Events, Foundries, TSMC

L.C. Lu TSMC Senior Fellow and Vice President, Research and Development Design & Technology Platform (1)
Dr. L.C. Lu is Vice President of Research & Development / Design & Technology Platform at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and a TSMC Senior Fellow.

L.C. leads efforts in design enablement, ensuring that the company can meet the diverse and evolving requirements of its global customer base. Prior to this, he headed the Design and Technology Platform organization starting in 2018.

Since joining TSMC in 2000, Dr. Lu has held multiple leadership positions in design services. He has worked closely with process R&D teams to pioneer Design and Technology Co-Optimization (DTCO), improving speed, power efficiency, and density in advanced process technologies. He has also collaborated extensively with ecosystem partners through the TSMC Open Innovation Platform (OIP), helping deliver comprehensive design solutions and intellectual property for a wide range of applications, including high-performance computing, automotive, RF, and advanced 2.5D and 3D designs.

Dr. Lu’s contributions have earned him significant recognition. He received Taiwan’s National Outstanding Manager Award in 2012 and was named a TSMC Senior Fellow in 2025. He is also one of the company’s most prolific inventors, holding more than 100 patents worldwide.

He earned his bachelor’s degree in electrical engineering from National Taiwan University, a master’s degree in computer science from National Tsing Hua University, and a Ph.D. in computer science from Yale University.

L.C.’s presentation focuses on advanced design-technology co-optimization (DTCO), packaging innovations, and AI-driven methodologies that enable continued scaling in performance, power, and area (PPA) for next-generation semiconductor systems. The discussion highlights how tightly coupled design and process innovations, along with system-level integration, are critical to sustaining Moore’s Law in the era of AI and HPC.

At the device and design level, TSMC emphasizes DTCO and design-driven cell (DDCL) innovations to achieve node-to-node scaling from N5 through N2 and into A14. The introduction of NanoFlex and NanoFlex Pro architectures enables flexible standard cell design with significant gains in efficiency. N2 NanoFlex achieves up to 50% speed improvement at constant voltage or 50% power reduction at constant performance compared to traditional cells. Building on this, A14 NanoFlex Pro introduces a 1.5× cell height merged oxide diffusion (OD) architecture, significantly improving OD utilization and enabling tighter placement of high-speed and low-power cells. This results in 10–15% speed gains and ~20% area reduction relative to N2, effectively delivering multi-node scaling benefits within a single generation.

https://x.com/SemiAnalysis_/status/2047888356701306916

Further enhancements in N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations. Hybrid dual-rail architectures reduce minimum operating voltage (Vmin) by over 200 mV compared to single-rail designs, achieving approximately 40% energy savings. N2U extends N2P with incremental improvements—3–4% higher performance or 8–10% lower power—while maintaining full compatibility with existing design rules and IP, ensuring smooth adoption for customers.

EDA readiness and AI integration are key enablers of these advanced nodes. TSMC collaborates closely with electronic design automation (EDA) partners to ensure tool readiness and to incorporate AI-enhanced workflows. Agentic AI systems are being deployed across design cycles to optimize block placement, routing, and performance, improving both productivity and design quality. These AI techniques are also applied to analog and RF design, enabling efficient migration across process nodes and accelerating time-to-market.

At the system level, TSMC’s advanced packaging technologies—particularly CoWoS, SoIC, and 3D Fabric—play a central role in enabling AI scaling. CoWoS technology continues to scale reticle size and integration capacity, allowing significant increases in compute density. From 2024 to 2029, the number of transistors in a single CoWoS system is projected to increase by 48×, driven by larger package sizes, increased system-on-chip (SoC) counts, and transition to advanced nodes such as TSMC A14.

Memory bandwidth scaling is similarly aggressive, with high-bandwidth memory (HBM) integration increasing both capacity and throughput. HBM stacks are expected to grow from 8 to 24, while I/O bandwidth per stack doubles and data rates increase significantly, resulting in an overall 34× bandwidth improvement. This scaling is supported by advancements in both DRAM technology and logic-based base dies fabricated on advanced nodes.

Interconnect performance is improved through finer pitch scaling in both 2.5D and 3D integration. In CoWoS, micro-bump pitch reduction enhances bandwidth density and energy efficiency, while in SoIC, scaling to ~4.5 µm bump pitch delivers up to 4× bandwidth density and substantial energy savings. Additionally, silicon photonics integration via CUPE optical engines provides high-speed, low-latency interconnects, achieving 5–10× power efficiency improvements and 10–20× latency reduction compared to traditional electrical links.

Power delivery and thermal management are identified as critical challenges in AI systems due to increasing compute density. TSMC addresses these through advanced capacitance solutions such as metal-insulator-metal (MIM) capacitors and embedded deep trench capacitors (eDDC), achieving over 10× improvements in capacitance density and reducing voltage droop significantly. Thermal optimization techniques—including improved packaging materials, hotspot spreading, and structural enhancements—reduce thermal resistance by up to 40%, ensuring reliable operation under high power conditions.

Bottom line: TSMC is advancing design methodologies through 3D IC design standardization and AI-driven automation. The introduction of “3D Blocks” as a modular design language aims to streamline 3D IC workflows and enhance collaboration across the ecosystem, with ongoing efforts toward IEEE standardization. Combined with generative AI and agent-based design optimization, these innovations promise substantial improvements in productivity and scalability for complex chip-package co-design.

Also Read:

Dr. Cliff Hou and the TSMC N2 Process Technology

TSMC Technology Symposium 2026 Overview