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Alchip Technologies Ltd., a global leader in high-performance computing (HPC) and artificial intelligence (AI) ASIC design and production services, continues its trajectory of rapid growth and technical leadership by pushing the boundaries of advanced-node silicon, expanding its global design capabilities, and building customer-centric solutions that differentiate at the packaging level. In a candid update from CEO Johnny Shen, three pillars emerged as central to Alchip’s strategy: technology leadership, talent deployment, and customer-driven business execution.
TECHNOLOGY: 2nm and 3nm
Alchip is preparing for a significant technology inflection with the introduction of 2nm design enablement, the first gate-all-around (GAA) transistor node. While 3nm (the final FinFET-based node) will dominate most production designs in 2025, a select few projects are advancing into 2nm, which introduces unique design complexities. These include significantly higher compute power requirements for final sign-off and verification.
During peak 3nm workloads, Alchip leveraged more than 500 servers; for 2nm, even larger compute infrastructures will be required. The company’s 2nm test chip taped out in 2024, with silicon results expected soon. These results will help quantify the PPA (power, performance, area) delta between 3nm and 2nm. While pure 2nm designs might be rare, hybrid approaches—with compute logic in 2nm and analog/mixed-signal components in 3nm chiplets—are becoming common among customers.
Alchip’s early 2nm work is already being validated by one of its more significant customers, who plans to initiate both a test chip and product chip kickoff, within 2025. This underscores Alchip’s credibility as a first-choice ASIC partner for leading-edge silicon.
TEAM: Strategic Global Expansion of Engineering Resources
With 86% of 2024 revenue originating from North America, and with global expansion considerations, Alchip is aggressively shifting its design workforce to Taiwan, Japan, and Southeast Asia. In Vietnam, where the company already employs 30 engineers, headcount is expected to grow to 70–80 by the end of 2025. Similarly, Malaysia’s team is expanding from 20 to approximately 50 engineers. By year-end, over half of Alchip’s engineering workforce will reside outside China.
This distributed R&D model not only ensures IP security and compliance with international regulations but also enables proximity to foundries, customers, and local talent pools. In the United States, Alchip is scaling up its Field Application Engineers (FAEs), Program Managers (PMs), and senior R&D experts to support a customer base that demands nuanced understanding of compute architecture, PPA trade-offs, and roadmap alignment.
For package and assembly support, much of the technical interface remains US-based, with Taiwan-based experts frequently dispatched to co-locate with customers when needed. Testing and product engineering disciplines remain centralized in Taiwan, where Alchip’s reputation as a top-tier semiconductor employer provides a strong pipeline of experienced hires.
BUSINESS: Record-Breaking Growth Driven by Differentiated Solutions
In 2024, Alchip delivered its seventh consecutive year of record financials, with revenue of $1.62 billion and net income of $200.8 million—each marking new highs. These numbers translate into a revenue-per-employee ratio of approximately $2.5 million, placing Alchip among the most productive companies in the semiconductor industry.
Core to this growth is the company’s differentiated package engineering. While customers rarely question Alchip’s ability to deliver on the compute side, most customer inquiries now revolve around packaging strategy. These include determining the optimal HBM stack configuration, interposer design, chiplet integration, thermal modeling, and overall system optimization.
Alchip has completed 18 CoWoS (Chip-on-Wafer-on-Substrate) designs, the most of any ASIC partner, according to TSMC. These designs have varied significantly by customer, each requiring unique interposer geometries, memory bandwidth targets, and form factor considerations. Johnny attributes this capability to Alchip’s focus on emerging, high-tech startups, whose need to innovate quickly forces the company to stay ahead of the technology curve.
This flexibility and deep design experience have made Alchip a go-to partner not only for startups, but also for established tech giants pursuing the next wave of AI and HPC performance.
Outlook: Enabling Tomorrow’s Compute Platforms
With 20–30 tape outs per year, Alchip maintains a rapid feedback loop that continuously hones its methodology, toolchains, and cross-functional workflows. As customers move toward 2nm GAA, 3DIC architectures, and multi-die systems, Alchip is positioning itself as a turnkey provider of silicon, packaging, and system-level integration expertise.
Its tight alignment with TSMC’s roadmap, along with a strategic pivot toward a distributed global engineering footprint, ensures that Alchip will remain a critical player in enabling the future of AI and HPC workloads. The company’s ability to combine advanced silicon design with deep system integration know-how is what makes it not just a service provider—but a true innovation partner.
The TSMC Technology Symposium recently kicked off in Santa Clara, with a series of events scheduled around the world. This event showcases the latest TSMC technology. It is also an opportunity for TSMC’s vast ecosystem to demonstrate commercial application on TSMC’s technology. There is a lot to unpack at an event like this. There are great presentations and demonstrations everywhere, but occasionally a company rises above the noise and grabs the spotlight with unique or memorable news.
My view is that Analog Bits stepped into the spotlight this year with cutting-edge analog IP on the latest nodes and a strategy that will change the way design is done. Let’s examine how Analog Bits steals the show with working IP on TSMC 3nm and 2nm and a new design strategy.
Blazing the Trail to 2nm
Working silicon demonstrations of TSMC’s CLN2P technology represent rare air at this TSMC event. Analog Bits recently completed a successful second test chip tapeout at 2nm, but the real news is the company also came to the show with multiple working analog IPs at 2nm. Six precision IPs were demonstrated, the locations of those blocks on the test chip is shown below and the finished chip pictured at the top of this post.
ABITCN2P – Test Chip Layout
What follows are some details from the cutting edge. Let’s begin with the wide range PLL. Features of this IP include:
Electrically programmable for multiple applications
Wide range of input and output frequencies for diverse clocking needs
Implemented with Analog Bits’ proprietary architecture
Low power consumption
Spread spectrum tracking capability
Requires no additional on-chip components or bandgaps, minimizing power consumption
Excellent jitter performance with optimized noise rejection
The figure below illustrates some power and jitter numbers. Note the jitter data is for the whole test setup, test chip output buffers, test board, measurement equipment, and not a de-embedded number of the PLL standalone.
PLL Jitter and Power
Next is the PVT sensor. IPs like this are critical for managing power and heat. There will be more on power management in a bit. Features of this IP include:
High accuracy thermometer is a highly integrated macro for monitoring temperature variation on-chip
Industry leading accuracy untrimmed, with easy trimming procedures
An additional voltage sample mode is included allowing for voltage monitoring
The block includes a simple-to-use digital interface that works with standard core and IO level power supplies
Implemented with Analog Bits’ proprietary architecture
Low power consumption
Demonstrations included showcasing the temperature accuracy and temperature and voltage linearity of the IP.
Next is a droop detector. Voltage droop is another key item for power management. It occurs when the current in the power delivery network (PDN) abruptly changes, often due to workload fluctuations. This effect can lead to supply voltage drops across the chip which can cause performance degradation, reduce energy efficiency, and even result in catastrophic timing failures. Feature of this IP include:
Integrated voltage reference for stand-alone operation
Easy to integrate with no additional components or special power requirements
Easy to use and configure
Programmable droop detection levels
Low power
Implemented with Analog Bits’ proprietary architecture
Requires no additional on-chip macros, minimizing power consumption
The next IP is an 18-40MHz crystal oscillator. Features for this IP include:
Pad macro that supports most industry standard crystals in the 18-40MHz range
Uses standard CMOS transistors
Power-down option for IDDQ testing
Oscillator by-pass mode option for logic testing
Self-contained ESD protection structure
And finally, the differential transmit (TX) and receive (RX) IP blocks. Features here include:
TX
Wide frequency range support up to 2,000 MHz output for diverse clocking needs
Implemented with Analog Bits’ proprietary architecture
Low power consumption
Requires no additional on-chip components or bandgaps, minimizing power consumption
RX
Differential clock receiver
Single-ended output to chip core
Wide ranges of input frequencies for diverse clocking needs
Implemented with Analog Bits’ proprietary architecture
Low power consumption
Programmable termination
Spread spectrum tracking capability
Requires no additional on-chip components or bandgaps, minimizing power consumption
On the Cutting Edge with 3nm IP
Four power management IPs from TSMC’s CLN3P process were also demonstrated at the show. The test chip these IPs came from is also pictured in the graphic at the top of this post. The IPs demonstrated include:
A scalable low-dropout (LDO) regulator. Features of this IP include:
Integrated voltage reference for precision stand-alone operation
Easy to integrate with no additional components or special power requirements
Easy to use and configure
Scalable for multiple output currents
Programmable output level
Trimmable
Implemented with Analog Bits’ proprietary architecture
Requires no additional on-chip macros, minimizing power consumption
The line regulation performance of this IP is shown in the figure below.
Next is a spread spectrum clock generation PLL supporting PCIe Gen4 and Gen5. Features of this IP include:
High performance design emphasis for meeting low jitter requirements in PCIe Gen4 and Gen5 applications
Implemented with Analog Bits’ proprietary LC architecture
Low power consumption
Spread spectrum clock generation (SSCG) and tracking capability
Excellent jitter performance with optimized noise rejection
Calibration code and bandgap voltage observability (for test)
Requires no additional on-chip components, minimizing power consumption
A high-accuracy thermometer IP using Analog Bits patented pinless technology was also demonstrated. Features of this IP include:
IP is a highly integrated macro for monitoring temperature variation on-chip
Industry leading accuracy untrimmed, with easy trimming procedures
An additional voltage sample mode is included allowing for voltage monitoring
The block includes a simple-to-use digital interface that works with just standard core and power supply saving customers analog routing and simplifying package design
Pinless technology means the IP is powered by the core voltage, no analog power pin is required
Low power consumption
Voltage linearity for this IP is shown in the figure below.
Voltage Linearity
And finally, a droop detector for 3nm. Features include:
Integrated voltage reference for stand-alone operation
Easy to integrate with no additional components or special power requirements
Easy to use and configure
Programmable droop detection levels
Low power
Implemented with Analog Bits’ proprietary architecture
Requires no additional on-chip macros, minimizing power consumption
Intelligent Power Architecture Launches a New Design Strategy
Innovation brings new challenges. A big design challenge is optimizing performance and power in an on-chip environment that is constantly changing, is prone to on-chip variation and is faced with all kinds of power-induced glitches. As multi-die design grows, these problems are compounded across many chiplets that now also need a high-bandwidth, space-efficient, and power-efficient way to communicate.
This problem cannot be solved as an afterthought. Plugging in optimized IP or modifying software late in the design process will not be enough. Analog Bits believes that developing a holistic approach to power management during the architectural phase of the project is the only path forward.
It is against this backdrop that the company announced its Intelligent Power Architecture initiative at the TSMC Technology Symposium. The company stated that its high-accuracy on-die PVT sensors, process performance monitors, integrated power-on resets, droop detectors, LDOs, and glitch catchers all work together with its low power SerDes, ADCs and pinless IP libraries to deliver a power management architecture that will meet the most demanding requirements. Pinless IP technology, invented by Analog Bits, will become even more critical to migrate below 3nm as all of the IP will work directly from the core voltage. The technology is already proven in production silicon on N5 and N3.
Analog Bits stated the company is already working with large, successful organizations that are building some of the most power-hungry chips in the world to achieve this goal. The mission now is to bring an intelligent power architecture to mainstream design for all companies. This work will be interesting to watch as Analog Bits re-defines the way advanced design is done.
Keep watching the company’s website as the strategy behind the Intelligent Power Architecture unfolds. And that’s how Analog Bits steals the show with working IP on TSMC 3nm and 2nm and a new design strategy.
The inaugural event for the 2025 TSMC Technology Symposium recently concluded in Santa Clara, California. This will be followed by events around the world over the next two months. We have summarized information from this event regarding process technology innovation and advanced packaging innovation. Overall, the A14 process node was deemed to define the most advanced technology available from TSMC. Recently, a presentation from the event was posted that discusses technology leadership, and in that presentation, what lies beyond A14. Seeing what’s around the next corner is always interesting. Let’s look at how TSMC describes technology innovation beyond A14.
The Presenter
Dr. Yuh Jier Mii
The presenter was Dr. Yuh-Jier Mii, EVP and Co-Chief Operating Officer at TSMC. Dr. Mii is an excellent presenter. He describes very complex work in language everyone can understand. His presentation builds on work he presented at last year’s IEDM event. Dr. Mii covered a lot of information. A link is coming. But first, I’d like to focus on his comments on innovation at TSMC beyond A14.
What Was Said
The broad focus of Dr. Mii’s discussion focused on new transistor architectures and new materials. He began by discussing device architectures. The current evolution is from FinFET to Nanosheet. Beyond these technologies, vertically stacked NFET and PFET devices, called CFETs is a likely scaling candidate. Beyond CFET, there are breakthroughs in channel material that can enable further dimensional scaling and energy reduction. These developments are summarized in the graphic above.
Dr. Mii reported that TSMC has been actively building CFET devices on silicon to enable the next level of scaling. TSMC presented its first CFET transistor at a 48nm gate pitch at IEDM 2023. This year at IEDM, TSMC presented the smallest CFET inverter. The figure below illustrates the well-balanced performance characteristics of this device up to 1.2V.
He explained that this demonstration achieved a significant milestone in CFET technology development that will help to drive future technology scaling.
Dr. Mii reported that great progress has also been made on transistors with 2D channel materials. TSMC has demonstrated the first electrical performance using a monolayer channel in stacked nanosheet architecture similar to the N2 technology. An inverter has also been developed using well-matched N and P channel devices operating at 1V. This work is summarized in the figure below.
Going forward, there are plans to continue to develop new interconnect technologies to improve interconnect performance. For copper interconnect, the plan is to use a new via scheme to reduce via resistance and coupling capacitance. Work is also underway on a new copper barrier to reduce copper line resistance.
Beyond copper, there is work underway on new metal materials with an air gap that could further reduce resistance and coupling capacitance. Intercalated Graphene is another new and promising metal material that could significantly reduce interconnect delay in the future. This work is summarized in the graphic below.
To Learn More
Dr. Mii covered many other topics. You can view his entire presentation here. And that’s how TSMC describes technology innovation beyond A14.
The worldwide TSMC 2025 Technology Symposium recently kicked off with the first event in Santa Clara, California. These events typically focus on TSMC’s process technology and vast ecosystem. These items were certainly a focus for this year’s event as well. But there is now an additional item that shares the spotlight – packaging technology. Thanks to the increase in heterogeneous integration driven in large part by AI, the ability to integrate multiple dies in sophisticated packages has become another primary driver for innovation. So, let’s look at what was shared at the pre briefing by Dr. Kevin Zhang and how TSMC brings packaging center stage with silicon.
A Growing Palette of Options
TSMC has taken advanced packaging well beyond the 2.5D interposer approach that is now quite familiar. The diagram above was provided by TSMC to illustrate the elements that comprise the TSMC 3DFabric® technology portfolio. According to TSMC, transistor technology and advanced packaging integration technology go hand-in-hand to provide its customers with a complete product-level solution.
On the left are the options for stacking or die-level/wafer-level integration. SoIC-P ( below) uses microbump technology to deliver down to a 16um pitch. Using bumpless technology (SoIC-X), you can achieve a few micron pitch. TSMC started with 9um and is now in production at 6um with more improvements to come, creating a monolithic-like integration density.
For 2.5/3D integration, there are many options available. Chip on Wafer on Substrate (CoWoS) technology supports both the familiar silicon interposer as well as CoWoS-L, which uses an organic interposer with a local silicon bridge for high-density interconnect. CoWos-R provides a pure organic interposer.
Integrated Fan-Out (InFO) technology began in 2016 for mobile applications. The platform has been expanded to support automotive applications as well.
There is also the newer System-on-Wafer (TSMC-SoW™) packaging. This technology broadens the integration scale to the wafer level. There is a chip-first approach (SoW-P), where the chip is put on the wafer and then an integrated RDL is built to bring the dies together. Or, there is a chip-last approach (SoW-X), where you first build the interposer at the wafer level and then add the chips across the wafer. This last approach can produce a design that is 40X larger than the standard reticle size.
High-performance computing for AI is clearly a major driver for advanced packaging technology. The first diagram below provided by TSMC, illustrates a typical AI accelerator application today that integrates a monolithic SoC with HBM memory stacks through a silicon interposer. Some major improvements that are coming for this type of architecture as shown on the next diagram.
The monolithic SoC is now replaced with a 3D stack of chips to address high-density compute requirements. HBM memory stacks are integrated with an RDL interposer. Integrated silicon photonics will also be part of the design to improve communication bandwidth and power. Integrated voltage regulators will also help to optimize power for this type of application.
Regarding power optimization, future AI accelerators can require thousands of watts of power, creating a huge challenge in terms of power delivery into the package. Integrated voltage regulators will help to tame this class of problem. TSMC has developed a high-density inductor which is a key component required to develop this class of regulator. So, a monolithic PMIC plus this Inductor can provide a 5X power delivery density (vs. PCB level).
There are many exciting new technologies on the horizon which will require all the packaging innovation discussed here. Augmented reality glasses is one example of a new product that will require everything discussed. A device like this will require, among other things, an ultra-low power processor, a high resolution camera for AR sensing, eNVM for code storage, a large main processor for spatial computing, a near-eye display engine, WiFi/Bluethooth for low latency RF, and a digital intensive PMIC for low power charging. This kind of product will set a new bar for complexity and efficiency.
While autonomous vehicles get a lot of attention, the demands of humanoid robots were also discussed. TSMC provided the graphic below to illustrate the significant amount of advanced silicon required. And the ability to integrate all of this into dense, power efficient packages is critical as well.
To Learn More
It was clear at the TSMC Technology Symposium that advanced processing and advanced packaging will need to work as one going forward to achieve the type of product innovation on the horizon. TSMC has clearly taken this challenge and is developing unified offerings to address the coming requirements.
At the pre-conference briefing, Dr. Kevin Zhang gave quite a few of us media types an overview of what will be highlighted at the 2025 TSMC Technical Symposium here in Silicon Valley. Since most of the semiconductor media are not local this was a very nice thing to do. I will be at the conference and will write more tomorrow after the event. TSMC was also kind enough to share Kevin’s slides with us.
The important thing to note is that TSMC is VERY customer driven so this presentation is based on interactions with the largest semiconductor manufacturing customer base the industry has ever seen, absolutely.
As you can imagine, AI is driving the semiconductor industry now not unlike what smartphones did for the last two decades. The difference being that AI consumes leading edge silicon at an alarming rate which is a good thing for the semiconductor industry. While AI is very performance centric, it must also be power sensitive. This puts TSMC in a very strong position from all of those years of manufacturing mobile SOCs for smartphones and other battery operated devices.
Kevin started with the AI revolution and how AI will be infused into most every electronic device from the cloud to the edge and will enable many new applications. Personally, I think AI will transform the world in a similar fashion as smartphones have but on a much grander scale.
Not long ago the mention of the semiconductor industry hitting $1T seemed like a dream. It is one thing for industry observers like myself to say it but it is quite another when TSMC does. There is little doubt in my mind that it will happen based on my observations inside the semiconductor ecosystem.
There have been some minor changes to the TSMC roadmap. It has been extended out to 2028 adding N3C and A14. The C is a compressed version meaning the yield learning curve is at a point where the process can be further optimized for density.
A14 will certainly be a big topic of discussion at the event. A14 is TSMC’s second generation of nanosheet transistor which is considered a full node (PPA) versus N2: 10-15% speed improvement at the same power, 25-30% power reduction at the same speed, and 1.2X logic density improvement. The first iteration of 14A does not have backside power delivery. It was the same with N2 which was followed by A16 with Super Power Rail (SPR). SPR for A14 is expected in 2029.
The TSMC 16A specs were updated as well. 16A is the first version of SPR for reduced IR drop and improved logic density. This has the transistor connection on the back. SPR is targeted at AI/HPC designs with improved signal routing and power delivery. A16 is on track for production in the second half of 2026. In comparison to N2P, A16 provides an 8-10% speed improvement at the same power, 15-20% power reduction at the same speed.
From what I have heard TSMC N2 is yielding quite well and is on track for production later this year. The big question is who will be the first customer to ship N2 product? Usually it is Apple but word on the street is the iPhones this year will again be using N3. I already have an N3 iPhone so I will skip this generation if that is the case. If Apple does an N2 based iPhone Max Pro this year then count me in!
TSMC N2P is also on track for production in the second half of 2026. As compared to N3E, N2P offers: 18% speed improvement at the same power, a 36% power reduction at the same speed, and a 1.2x density improvement.
The most interesting thing about N2 is the rapid growth of tape-outs between N5, N3, and N2. It really is astounding. Given that TSMC N3 was an absolute landslide for customer tape-outs I had serious doubts if we would ever see a repeat of that success but here we are. Again, in the past mobile was the driver for early tape-outs but now we have AI/HPC as well.
Finally, as Kevin said, TSMC N3 is the last and best FinFET technology available on such a massive scale with N3, N3E, N3P, N3X, N3A, and now N3C. Yet, N2 tape-outs beat N3 in the first year and the second year even more so. Simply amazing. I guess the question is who is NOT using TSMC N2?
The second part of the presentation was on packaging which will be covered in another blog. After the event I can provide even more details and get a feeling for the vibe at the event from the ecosystem. Exciting times!
UPDATE: TSMC is sharing recordings of the presentations HERE.
At IEDM held in December 2024, TSMC presented: “2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the authors are:
Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng, M. Wang, PW Wang, CP Lin, KF Yu, WY Lee, HK Chen, DW Lin, BR Yang, CC Yeh, CT Chan, JM Kuo, C-M Liu, TH Chiu, MC Wen, T.L. Lee, CY Chang, R. Chen, P-H Huang, C.S. Hou, YK Lin, FK Yang, J. Wang, S. Fung, Ryan Chen, C.H. Lee, TL Lee, W. Chang, DY Lee, CY Ting, T. Chang, HC Huang, HJ Lin, C. Tseng, CW Chang, KB Huang, YC Lu, C-H Chen, C.O. Chui, KW Chen, MH Tsai, CC Chen, N. Wu, HT Chiang, XM Chen, SH Sun, JT Tzeng, K. Wang, YC Peng, HJ Liao, T. Chen, YK Cheng, J. Chang, K. Hsieh, A. Cheng, G. Liu, A. Chen, HT Lin, KC Chiang, CW Tsai, H. Wang, W. Sheu, J. Yeh, YM Chen, CK Lin, J. Wu, M. Cao, LS Juang, F. Lai, Y. Ku, S.M. Jang, L.C. Lu- with Jeffrey Yeap presenting the work.
This paper continued TSMC’s trend over the last several years of presenting marketing papers at IEDM instead of technical papers. In fact, this paper took the trend even further, there are no pitches in the paper, no SRAM cell size, and that graphs are all relative performance graphs without real units. Although the paper doesn’t present the kind of technical details that would typically be included in an IEDM paper, it does paint a picture of a process ready for 2025 production and the session was packed.
In this review we will take the few substantive details that are in the paper as well as our own analysis and present how the process compares to competing 2nm class processes.
In terms of the overreaching Power, Performance, and Area (PPA), the paper states that the process delivers a 30% power improvement or 15% performance gain and >1.15x density versus the previous 3nm node. Note: the 3nm paper reference suggests this is in comparison to N3E, not N3.
Power
At the 14nm (Samsung)/16nm (TSMC) node Samsung and TSMC both produced the Apple A9 processors. Measurements by Tom’s hardware found the Samsung version had slightly better power performance compared to TSMC. We believe the A9 was designed for Samsung first so that may simply reflect a design that is more optimized for Samsung that was ported to TSMC, nevertheless, the power was very close between the two. Going forward from 14nm/16nm, to 10nm, 7nm, 5nm, 3nm, and now 2nm Samsung and TSMC have both provided relative power improvement for each node versus the previous node.
We have been able to compare the Samsung and TSMC at 3 different nodes since the 14/16nm comparison and our extrapolations have been consistent with those values.
At 10nm TSMC provided a larger power reduction than Samsung and maintained that lead until 3nm where Samsung Gate All Around (GAA) provided a large enough improvement to mostly close the gap to TSMC’s 3nm FinFET process in power (GAA versus FinFET is expected to provide a greater power improvement).
TSMC 2nm announced power improvement of 30% versus 3nm is greater than Samsung’s 25% improvement and TSMC once again maintains a lead.
Specific power factor numbers are available in the full article available with free registration on the TechInsights platform here.
During the presentation of the paper, graphs were shown of power efficiency and performance per watt versus node. The power efficiency graph was in one version of the paper although it is not in the “final” version of the paper published in the proceeding. Thankfully we captured the power efficiency graph because it is very interesting to analyze, see figure 1.
Figure 1. TSMC Power Efficiency.
We took the graph image, pulled it into Excel and created an Excel graph overlaying it with the 28nm bar normalized to 1 and then entering values for the other bars until they matched the graph. If we then build a set of bars starting at 28nm = 1 scaled up based on the TSMC announced node to node power improvements we get a total improvement of less than 9x. Nodes from N28 to N10 match well but from N7 on the bars on the graph show more improvement per node than TSMC has announced. Just the N3 to N2 bars on the graph show a 55% improvements versus the announced 30% improvement.
Figure 2 is in the full article available with free registration on the TechInsights platform here.
It isn’t clear what may be driving this difference, but it is a big disconnect. This may be why the graph was removed from the final paper.
Performance
Similar to the power analysis above, at Samsung 14nm/TSMC 16nm the Apple A9 processor had identical performance on the 2 processes. Normalizing both processes to 1 and applying the announced node to node performance improvements from both companies it is possible to compare performance per node. It has also been possible to use an Intel 10SF versus AMD processors on TSMC 7nm process, to add Intel to the analysis and forward calculate based on Intel performance by node announcements.
We have been able to check our extrapolations at 3 nodes for Samsung and TSMC since the 16/14nm nodes as well as Intel at 2 nodes and those checks have confirmed our extrapolations are tracking correctly.
Based on this analysis it is our belief that Intel 18A has the highest performance for a 2nm class process with TSMC in second place and Samsung in third place.
Our performance index values are in the full article available with free registration on the TechInsights platform here.
Area
The third part of PPA is area. We analyze two “area” related factors, one is high density logic cell transistor density and the second is SRAM cell size. TechInsights has done detailed reverse engineering work on TSMC N3E process and we have all the pitches necessary to calculate our standard high density logic cell transistor density. Similarly, we have analyzed Samsung SF3E and SF3. Both TSMC in this paper and Samsung in public statements have provided density improvement values for 2nm. In the case of Intel we have used our own estimated pitches to do a density comparison. For high density logic cells TSMC is well ahead of Samsung and Intel on density, Intel is second, and Samsung is third.
The high density logic cell transistor density is in the full article available with free registration on the TechInsights platform here.
As previously mentioned, the TSMC paper does not include SRAM cell sizes, however there is a graph of SRAM density versus node, see figure 3.
Figure 3. SRAM Array Density Versus Node.
The problem with this is an SRAM array includes not only the SRAM cell but also overhead, for example 7nm has 25.0 Mb/mm2, the SRAM cell size at 7nm was 0.0270um2. If you multiply 25.0Mb by the SRAM cell size, you get 0.675mm2. The difference between 1.000 and 0.675mm2 is the overhead and it isn’t constant from node to node, see table 1.
The SRAM cell size analysis is in the full article available with free registration on the TechInsights platform here.
Yield
Yield is a hot topic these days with lot of reports about Samsung struggling with yield at 3nm and losing customers due to low yield, there have also been some recent reports that Intel’s 18A yield is 10%.
In the paper TSMC reports that a 256Mb SRAM array has >80% average yield and >90% peak yield. These yields at this point in development indicate excellent defect densities. There are other yield components beside those tested in an SRAM array, but these are impressive results.
With respect to Intel’s 10% yield report, we have had two separate credible sources that tell us that simply isn’t true, that yields are much better than that. The other things about a report of 10% yield is how big/what is the die and at what point in development was that yield seen if it is even true. Our belief based on our sources is the 10% reported yield is either wrong or old data.
Wafer price
Another number that has been widely circulated is that TSMC is going to charge $30,000 per wafer for 2nm.
TechInsights produces the world’s leading cost and price models for semiconductors. Prior to 3nm entering production we were projecting <$20,000 per wafer and a few customers contacted us insisting 3nm prices would be $20,000 to $25,000 per wafer. Once 3nm entered production we were able to run our proprietary forensics on TSMC’s financials and determine we were correct, and the volume price was <$20,000/wafer by thousands of dollars.
To go from a price of <$20,000/wafer for 3nm wafers to $30,000/wafer for 2nm wafers is a >1.5x price increase for a 1.15x density improvement, that is a dramatic increase in transistor cost and it raises the question of who would pay that, our price estimates are <$30,000/wafer. There have also been reports that Apple who is typically TSMC’s lead customer for each node may be forgoing initial 2nm use due to price although we have also heard push back on that.
Another element to this discussion is what volumes the pricing is for TSMC’s high volume wafer price is a lot lower than their low volume wafer price, so volume needs to be considered in any discussion. In general, we believe $30,000 is higher than the average to high volume pricing will be.
If TSMC prices 2nm wafers at $30,000/wafer they will create a lot of pressure for customers to switch to Intel and Samsung for 2nm class wafer supplies.
Backside Power Delivery
The TSMC paper does not address backside power delivery but competing 2nm processes will be implementing backside power delivery.
Intel 18A will have backside power delivery – with a 2025 ramp Intel will be the first to implement this technology. In 2026 Samsung SF2P process is due to also implement backside power delivery. Finally, TSMC is not expected to implement backside power delivery on their 2nm process variants at all and will wait until 2027 (recent reports are that this is being pulled in to 2026) to implement it on their A16 process. The A16 backside power delivery is expected to be a direct backside connection that can provide smaller track heights than Intel’s and likely Samsung’s implementation.
Since Intel is the most performance focused of the three companies it makes sense, they are implementing backside power delivery first.
Another interesting thing we are hearing about backside power delivery is that foundry HPC customers want it but mobile customers don’t due to cost.
For multiple nodes we may see nodes with and without backside power delivery and given the effect it has on metal 0 the design rules would likely be different. In addition to this for the highest performance we expect molybdenum to be introduced first for vias and later from critical interconnect. This could lead to nodes splitting between backside power delivery and molybdenum metallization for HPC and no backside power and copper metallization for mobile.
Other
One final interesting item in the paper is the comment about “flat passivation”. Many processes have a top aluminum metal layer and passivation follows the metal contours, if something like hybrid bonding is desired the wafer surface must be flat. Flat passivation is presumably a planarized top layer to enable bonding.
Conclusion
TSMC has disclosed a 2nm process likely to be the densest available 2nm class process. It also appears to be the most power efficient at least when compared to Samsung. In terms of performance, we believe Intel 18A is the leader. The early yield reports appear promising, but the reports of $30,000/wafer pricing do not in our opinion represent acceptable value for the process and may present an opportunity for Intel and Samsung to capture market share . TSMC 2nm should be in production in the second half of this year.
There was a lot of discussion at IEDM about the coming shift to gate-all-around (GAA) transistor structures. This new device brings many benefits to continue device scaling, both at the monolithic device level as well as for multi-die design. The path to GAA is not simple, there are new material, process and design considerations to tame. TSMC has devoted a substantial amount of effort here. Let’s look at some of the details disclosed when TSMC unveils the world’s most advanced logic technology at IEDM.
About the Presenter
Dr. Geoffrey Yeap
Dr. Geoffrey Yeap presented 2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications on Monday at IEDM. He is Vice President, TSMC R&D Advanced Technology. Geoffrey has been at TSMC for almost nine years and has also led advanced work at Qualcomm, Motorola Mobility, AMD, and the University of Texas System Center for Supercomputing.
Geoffrey explained that the work he was presenting spanned four years and involved many staff members in TSMC’s Global R&D Center.
Presentation Overview
According to the IEDM press kit, this late news paper presents the world’s most advanced logic technology. As the title says, the work is focused on a leading edge 2nm CMOS platform technology (N2) that has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. Geoffrey explained that since the generative AI break-through in Q1’23, AI together with 5G-advanced mobile and HPC have created a huge appetite in the semiconductor industry for best-in-class energy-efficient logic technology and this work responds to that need.
Geoffrey described the state-of-art TSMC N2 technology and its successful transition into NS platform technology with acceleration of >140x energy-efficient compute from 28nm to N2, as depicted in the graphic at the top of this post. The N2 logic technology features energy-efficient gate-all-around nanosheet transistors, middle-of-line and backend-of-line interconnects with the densest SRAM macro of ~38Mb/mm2. N2 delivers a full node benefit from the previous 3nm node in offering 15% speed gain or 30% power reduction with >1.15x chip density increase.
The N2 platform technology is equipped with new copper scalable RDL interconnect, flat passivation and TSVs. It co-optimizes holistically with TSMC’s 3DFabric™ technology enabling system integration/scaling for the target AI/mobile/HPC product designs.
Geoffrey reported that N2 has successfully met wafer-level reliability requirements and passed 1,000 hours of HTOL qualification with high yielding 256Mb HC/HD SRAM, and logic test chip (>3B gates) consisting of CPU/GPU/ SoC blocks. N2 is currently in risk production. N2 platform technology is scheduled for mass production in the second half of 2025. N2P, a 5% speed enhanced version of N2 with full GDS compatibility, is targeted to complete qualification in 2025 and go to mass production in 2026.
Some More Details
From a platform perspective, Geoffrey provided some details about the N2 NanoFlex™ technology architecture. System technology co-optimization (STCO) was utilized with smart scaling features rather than brute-force design rule scaling which can drastically increase process cost and inadvertently causes critical yield issues. Extensive STCO coupled with smart scaling of major design rules (e.g., gate, nanosheet, MoL, Cu RDL, passivation, TSVs) was performed in optimizing the technology to achieve the target PPA.
He pointed out that co-optimization with 3DFabric SoIC 3D-stacking and advanced packaging technology (INFO/CoWoS variants) was done, thereby accelerating system integration/scaling for AI/mobile/HPC product designs. N2 NanoFlex standard cell innovation offers not only nanosheet width modulation but also a much-desired design flexibility of a multi-cell architecture.
This capability delivers N2 short cell libraries for area and power efficiency. He explained that selective use of tall cell library elements lifts the frequency to meet design targets. With six Vt offerings spanning 200mV, N2 provides unprecedented design flexibility to satisfy a wide spectrum of energy-efficient compute applications at the best logic density. The figure below illustrates some of the benefits of this approach for an Arm-based design.
N2 NanoFlex HD cell benefits
Geoffrey explained that N2 nanosheet technology exhibits substantially better performance/Watt than FinFET at the low Vdd range of 0.5V- 0.6V. Emphasis is placed on low Vdd performance/Watt uplift through process and device continuous improvements resulting in a 20% speed gain and 75% lower stand-by power at 0.5V operation. N2 NanoFlex coupled with multi-Vt provides unprecedented design flexibility to satisfy a wide spectrum of energy-efficient compute applications at the most competitive logic density.
Geoffrey went into more details on the SRAM, logic test chip and qualification and reliability. This was an impressive presentation. The N2 technology platform brings a lot of new capability to the table for future innovation. And that’s some of the details about how TSMC unveils the world’s most advanced logic technology at IEDM.
The main program for the 70th IEDM opened on Monday morning in San Francisco with an excellent keynote from Dr. Yuh-Jier Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. Dr. Mii joined TSMC in 1994. Since then, he has contributed to the development and manufacturing of advanced CMOS technologies in both fab operations and R&D. In 2022, he received the IEEE Frederik Philips Award recognizing his outstanding accomplishments in the management of research and development. He holds 34 patents globally, including 25 US patents, and holds a B.S. in electrical engineering from National Taiwan University, as well as an M.S. and Ph.D. in Electrical Engineering from the University of California, Los Angeles (UCLA). He treated the audience to a broad view of technology innovation in his keynote. Let’s look at how IEDM opens with a big picture keynote from TSMC’s Yuh-Jier Mii.
About IEDM
To begin, that wasn’t a typo above. The 70th annual IEEE International Electron Devices Meeting (IEDM) just concluded. This incredibly long-lived conference began tracking technology innovation in the vacuum tube era. For seven decades the event has tracked semiconductor and electronic device technology, design, manufacturing, physics, and modeling. This year’s event had a record high number of submissions at 763 and a record number of accepted papers at 274.
The figure below summarizes the growth of this premier conference over the years.
2024 IEDM paper statistics
About the Keynote
Dr. Yuh-Jier Mii
Dr. Mii began his keynote with a short but compelling video that provided an overview of some of the innovations that have occurred in the semiconductor industry in general, and some of the advances contributed by TSMC in particular. All of this is driving the development of a trillion-transistor system in the near future. These trends are summarized in the graphic at the top of this post.
Dr. Mii touched on five key areas in his talk. I will provide a summary of his remarks. He began with a semiconductor industry & market outlook (I). AI is poised to play a key role in the industry’s growth as we move toward one trillion dollars in revenue by 2030. He projected that high-performance computing will contribute 40% of this number, mobile 30%, automotive 15%, and IoT 10%. He discussed the how ubiquitous AI technology is becoming across many products and markets. Generative AI and large language models are contributing to this growth and the complexity of the models for these new applications and the associated training required present substantial new challenges.
He pointed out that these new applications will require gigawatts of power within a few years. Reducing power consumption will be critical to allow these applications to flourish and new device technology and architectural advances will be needed.
Next, Dr. Mii discussed advanced logic technologies (II). He described the industry’s move from planar devices to FinFETs and most recently nanosheet technology for gate-all-around devices at 2nm. Patterning also advanced from immersion lithography to EUV and multi-patterning EUV. Design technology co-optimization, or DTCO has also helped to bring technology to new levels. For example, backside power delivery has helped to reduce power and increase density.
Regarding logic technology frontiers (III), Dr. Mii discussed the evolution from FinFET to nanosheet FET to vertically stacked complimentary or CFET architectures. He explained that the CFET approach holds great promise to allow continued Moore’s Law scaling with its 1.5 – 2X density improvement when compared to nanosheet devices. He described the work going on at TSMC to make CFETs a reality. At this year’s IEDM, TSMC is presenting the first and smallest CFET inverter at a 48nm pitch.
Dr. Mii explained that beyond CFET, the ongoing quest for higher performance and more energy-efficient logic technologies necessitates an accelerated search for channel materials that go beyond those based on silicon. He explained that carbon nanotubes (CNTs) and transition metal dichalcogenides (TMDs) have garnered significant interest due to both their physical and electronic properties. In the area of interconnects, he discussed a new 2D material that is being explored as a superior alternative to copper. This material shows lower thin film resistivity than copper at reduced thicknesses, helping to mitigate line resistance increases in scaled geometries and enhance overall performance.
Dr. Mii then moved to a discussion of system integration technologies (IV). While pushing 2D technology scaling to enable better transistors and higher packing density in monolithically integrated SoCs is important, so are innovations beyond the chip level to extend integration into the heterogenous domain.
He explained that advanced silicon stacking and packaging technologies, including SoIC, InFO, and CoWoS® continue to aggressively scale down the chip-to-chip interconnect pitch, offering the potential to improve 3D interconnect density by another six orders of magnitude. These trends are summarized in the figure below.
Advanced silicon stacking and packaging technologies
Dr. Mii discussed an emerging System-on-Wafer (SoW) technology, where all the chiplets and HBM memories for an entire system can be integrated directly on a 12-inch wafer. He explained that this approach can deliver an additional 40X compute improvement when compared to the most advanced data center AI accelerator today. Optical interconnect was also discussed, which can provide 20X more power efficiency than copper interconnect. Vertical stacking of logic and optical transceivers will help deliver these improvements. He explained that today the laser light source is outside the chip, but efforts are underway to integrate the laser on chip as well.
Dr. Mii concluded with a discussion of specialty technologies (V). Many of the items discussed here are high frequency or analog in nature to accommodate the interface between the digital and analog (real) world. He discussed innovations spanning N16 to N4 to accommodate the increased demands of new standards for WiFi.
Advances in embedded non-volatile RAM were also discussed in this part of the keynote. The benefits and challenges of both MRAM and RRAM were covered. CMOS image sensors were also discussed. This is a critical technology for automotive applications. As pixel size decreases, new approaches are needed to maintain sensitivity and dynamic range. Dr. Mii described work to separate the photo diode from the pixel device and re-integrate them using 3D wafer-to-wafer stacking.
Summary
Dr. Mii concluded by observing that semiconductor innovations, encompassing advances in device technology, system-level scaling, and customer-specific design ecosystems will remain pivotal in driving rapid technological progress in the era of AI. He pointed out that TSMC is actively exploring a new array of innovations for future generations of technology, system integration platforms, and design ecosystems. These efforts will be crucial in meeting the increasing societal demands for energy-efficient, data-intensive computing in the coming decades. He invited the audience to join in this important collaboration. And that’s how IEDM opens with a big picture keynote from TSMC’s Yuh-Jier Mii.
The TSMC Open Innovation Platform (OIP) Ecosystem Forum has become the industry benchmark when it comes to showcasing industry-wide collaboration. The extreme design, integration and packaging demands presented by multi-die, chiplet-based design have raised the bar in terms of required collaboration across the entire supply chain. World-class development and collaboration were on display at the recent event, which was held in Santa Clara on September 25, 2024. A critical technology required for success is enabling IP, in particular for sensing and power management. Analog Bits showcased substantial capabilities here. Let’s examine some of the work presented to see how Analog Bits builds a road to the future at TSMC OIP.
IP Development Progress
Analog Bits discussed some of the unique challenges advanced chip and multi-die design presents. Multi-domain sensing was discussed, along with the additional challenge of non-uniform thermal distributions. Real-time monitoring is another requirement. If the face of all this, calibration complexity, voltage supply noise, and crosstalk must all be dealt with as well.
Analog Bits portfolio of on-die sensing IP was presented, including:
PVT Sensors – integrated and pinless
Power on reset and over current detection macros
Power supply detectors that include:
Fast detecting glitch
Synchronized droop detection with filtering and differential sensing
The benefits of a comprehensive on-die sensing IP portfolio were also discussed. At the top of the list is improved power efficiency. A good approach here also prevents overheating and minimizes thermal stress. The overall benefits of enhanced reliability and improved yield also come into play.
Power management is also a key benefit. Things like voltage scalability, voltage spike, and droop protection are examples. Better integration that results in space savings is an added benefit.
Analog Bits presented a significant amount of silicon data based on a TSMC N3P test chip. The graphic at the stop of this post is an overview of what’s on this chip. There were many impressive results to show. Here is a list of some of them:
Temperature linearity and precision for the High-Accuracy Thermometer
Linearity and precision for the high-accuracy Voltage Sensor
Measured trigger voltage vs. threshold and untrimmed threshold accuracy for the Droop Detector
An overview of Low-Dropout (LDO) regulator development
Regarding the LDO, here is a summary of the program:
First LDO modules proven in silicon
Latest N3 test-chip taped out Q2 2024
Packaging and initial bring up Q1 2025
Automotive planned for mid-2025
Here is an example of the data presented. The plot is showing Voltage Sensor accuracy with the following parameters: VDDA: 1.2V, VDD: 0.75V, Corner: TT.
Voltage Sensor Accuracy
IP Collaboration Progress
OIP is all about ecosystem collaboration, so Analog Bits teamed with Arm to present an impressive presentation entitled, Optimized Power Management of Arm CPU Cores with Integrated Analog Bits Power Management and Clocking IP’s. The presenters were Lisa Minwell, Director of Technology Management at Arm and Alan Rogers, President at Analog Bits.
The once-in-a-generation transformation occurring in digital infrastructure was discussed. Complexity increases in data center SoC’s, coupled with AI deployment has made energy efficiency a central issue. It was pointed out that advanced chip and chiplet-based designs in 3nm and 2nm are integrating many Arm Neoverse cores.
The need for managing power to these cores on a granular level is getting increasingly important. The traditional methods of using off-chip LDO and power sensors no longer scales. A new approach is needed.
The work Analog Bits and Arm have done on several integrated power management and clocking IPs was presented. Arm customers can readily use these solutions in N3P and soon in N2P. LDO regulator IPs were also discussed to efficiently manage the large absolute and dynamic current supplies to Arm CPU cores.
A case study of how CPU cores seamlessly integrate with Analog Bits LDO and Power Glitch Detector IPs, along with integrated clocking capabilities was also presented. The implications of this work is substantial for advanced data center applications.
To Learn More
I have presented some of the highlights of Analog Bits presence at TSMC OIP. There is a lot more to the story, and you find out more about Analog Bits industry impact on SemiWiki here. You can also check out the company’s website here. And that’s how Analog Bits builds a road to the future at TSMC OIP.
At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the design process for these cutting-edge solutions has been critical, and 3DBlox is central to this mission. 3DBlox is an innovative framework inclusive of a standardized design language, introduced by TSMC aimed at addressing the complexities of 3D integrated circuit (3DIC) design. The following is a synthesis of that talk, delivered by Jim Chang, Deputy Director at TSMC for the 3DIC Methodology Group.
Progress from 2022 to 2023: Laying the Foundations for 3DBlox
In 2022, TSMC began exploring how to represent their 3DFabric offerings, particularly CoWoS (Chip-on-Wafer-on-Substrate) and INFO (Integrated Fan-Out), which are critical technologies for 3DIC. CoWoS integrates chips using a silicon interposer, while INFO uses RDL (Redistribution Layer) interposers. TSMC combined these approaches to create CoWoS-R, replacing the silicon interposer with RDL technology, and CoWoS-L, which integrates local silicon interconnects.
With these building blocks in place, TSMC realized that they needed a systematic way to represent their increasingly complex technology offerings. This led to the creation of 3DBlox, which provided a standard structure for representing all possible configurations of TSMC’s 3DFabric technologies. By focusing on three key elements—chiplets, chiplet interfaces, and the connections among interfaces—TSMC was able to efficiently model a wide range of 3DIC configurations.
By 2023, TSMC had honed in on chiplet reuse and design feasibility, introducing a top-down methodology for early design exploration. This methodology allowed TSMC and its customers to conduct early electrical and thermal analysis, even before having all the design details. Through a system that allowed for chiplets to be mirrored, rotated, or flipped while maintaining a master list of chiplet information, TSMC developed a streamlined approach for design rule checking across multiple chiplets.
Innovations in 2024: Conquering Complexity with 3DBlox
By 2024, TSMC faced the growing complexity of 3DIC systems and devised new strategies to address it. The key innovation was breaking down the 3D design challenge into more manageable 2D problems, focusing on the Bus, TSVs (Through-Silicon Vias), and PG (Power/Ground) structures. These elements, once positioned during the 3D floorplanning stage, were transformed into two-dimensional issues, leveraging established 2D design solutions to simplify the overall process.
Key Technology Developments in 2024
TSMC’s focus on maximizing 3DIC design productivity in 2024 revolved around five major areas of development: design planning, implementation, analysis, physical verification, and substrate routing.
Design Planning: Managing Electrical and Physical Constraints
In 3DIC systems, placing the Bus, TSVs, and PG structures requires careful attention to both electrical and physical constraints, especially Electromigration and IR (EMIR) constraints. Power delivery across dies must be precise, with the PG structure sustaining the necessary power while conserving physical resources for other design elements.
One of TSMC’s key innovations was converting individual TSV entities into density values, allowing them to be modeled numerically. By using AI-driven engines like Cadence Cerebrus Intelligent Chip Explorer and Synopsys DSO.ai, TSMC was able to explore the solution space and backward-map the best solutions for bus, TSV, and PG structures. This method allowed designers to choose the best tradeoffs for their specific designs.
Additionally, chip-package co-design was emphasized in 2024. TSMC collaborated with key customers to address the challenges of coordinating between the chip and package teams, which previously operated independently. By utilizing 3DBlox’s common object format and common constraints, teams could collaborate more efficiently, settling design constraints earlier in the process, even before Tech files were available.
Implementation: Enhancing Reuse and Hierarchical Design
As customers pushed for increased chiplet reuse, TSMC developed hierarchical solutions within the 3DBlox language to support growing 3DIC designs. With the increasing number of alignment marks required to align multiple chiplets, TSMC worked closely with EDA partners to identify the four primary types of alignment markers and automate their insertion in the place-and-route flow.
Analysis: Addressing Multi-Physics Interactions
Multi-physics interactions, particularly related to thermal issues, have become more prominent in 3DIC design. TSMC recognized that thermal issues are more pronounced in 3DIC than in traditional 2D designs due to stronger coupling effects between different physical engines. To address this, TSMC developed a common database that allows different engines to interact and converge based on pre-defined criteria, enabling efficient exploration of the design space.
One of the critical analysis tools introduced in 2024 was warpage analysis, crucial as the size of 3DIC fabric grows. TSMC developed the Mech Tech file, defining the necessary information for industry partners to facilitate stress simulation, addressing a gap in warpage solutions within the semiconductor industry.
Physical Verification: Ensuring Integrity in 3DIC Designs
TSMC tackled the antenna effect, a manufacturing issue where metal may accumulate plasma charges that can penetrate gate oxides via TSVs and bumps. By collaborating with EDA partners, TSMC created a design rule checking (DRC) deck that models and captures the antenna effect, ensuring it can be accounted for during the design process.
In 2024, TSMC also introduced enhancements in layout vs. schematic (LVS) verification for 3DIC systems. Previously, LVS decks assumed a one-top-die, one-bottom-die configuration. However, 3DBlox’s new automated generation tools allow for any configuration to be accurately verified, supporting more complex multi-die designs.
Substrate Routing: Tackling the Growing Complexity
As 3DIC integration grows in scale, so does the complexity of substrate routing. Substrate design has traditionally been a manual process. The growing size of substrates, combined with the intricate requirements of modern 3DIC designs, necessitated new innovations in this space.
TSMC’s work on Interposer Substrate Tech file formats began three years ago, and by 2024, they were able to model highly complex structures, such as the inclusion of tear drops in the model. This advancement offers a more accurate and detailed representation of substrates, crucial for the larger and more intricate designs emerging in the 3DIC space. TSMC worked with their OSAT partners through the 3DFabric Alliance to support this format.
Summary: 3DBlox – Paving the Way for 3DIC Innovation
TSMC’s 3DBlox framework has proven to be a crucial step in managing the complexity and scale of 3DIC design. From early exploration and design feasibility in 2023 to breakthroughs in 2024 across design planning, implementation, analysis, physical verification, and substrate routing, TSMC’s innovations are paving the way for more efficient and scalable 3DIC solutions. As the industry moves toward even more advanced 3D integration, the 3DBlox committee announced plans to make the 3DBlox standard publicly available through IEEE. 3DBlox will continue to play a vital role in enabling designers to meet the increasing demands of semiconductor technology for years to come.
