Posted on

AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation

AI-Driven DRC Productivity Optimization: Insights from Siemens EDA’s 2025 TSMC OIP Presentation
by Daniel Nenni on 12-09-2025 at 10:00 am
Categories: AI, EDA, Events, Siemens EDA, TSMC

AI Driven DRC Productivity Optimization Siemens AMD TSMC

 

In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence is revolutionizing this process. Delivered by David Abercrombie, Sr. Director of Calibre Product Management at Siemens EDA, alongside AMD experts Stafford Yu and GuoQin Low, the talk highlights collaborative advancements with TSMC and AMD to enhance productivity across understanding, fixing, debugging, and collaboration in DRC sign-off.

The presentation opens with an overview of Siemens EDA’s new AI Workflow System, designed to boost the entire EDA ecosystem. This system integrates knowledge capture, next-gen debug platforms, AI debug assistance, and automated fixing, ultimately optimizing DRC sign-off. Central to this is the Siemens EDA AI System, an open, secure platform deployable on-premises or in the cloud. It features a GenAI interface, a knowledge base, and a data lake that amalgamates Siemens EDA data, Calibre-specific data, and customer inputs. Powered by LLMs, ML models, and data query APIs, it enables intelligent solutions across tools like Calibre, Aprisa, and Solido. Key benefits include a single installation process, flexibility for customer integrations, and support for assistants, reasoners, and agents. This infrastructure ensures AI tools are hosted on customer hardware, maintaining data security while accelerating workflows.

A major focus is on boosting user understanding through AI Docs Assistant and Calibre RVE Check Assist. The AI Docs Assistant allows users to query Siemens EDA tool documentation via browser or integrated GUIs, providing instant answers with RAG-generated citations. It supports specific tools and versions, includes company documentation, and collects feedback for continuous improvement. Integrated with Calibre’s Results Viewing Environment (RVE) and Vision AI, it streamlines access to knowledge. Complementing this, Calibre RVE Check Assist leverages TSMC’s Design Rule Manual (DRM) data, embedding precise rule descriptions and specialized images directly into the RVE. This enhances designers’ comprehension of rule checks, improving debugging experiences and productivity. Additionally, RVE Check Assist User Notes facilitate in-house knowledge sharing: designers capture fixing suggestions and images in RVE, storing them in a central database within the EDA AI Datalake. This shared repository allows organization-wide review, enhancing DRC-fixing flows by leveraging collective expertise.

Shifting to automated fixing, the presentation details Calibre DesignEnhancer, an analysis-based tool for sign-off DRC-clean modifications on post-routed designs. It includes modules like DE Via, which maximizes via insertion to reduce IR drop and boost robustness, and DE Pge, which enhances power grids by adding Calibre nmDRC-clean interconnects for better EM and IR performance. The engine supports LEF/DEF formats and outputs incremental, full, or ECO DEF files, integrating seamlessly with Place-and-Route tools. Its infrastructure handles simple and complex metal rules, such as spacing (M.S., V#.S.), enclosure (M.EN., V.EN.), and forbidden patterns (EFP.M., EFP.V.), considering connectivity and rule dependencies. Examples illustrate fixes like expanding or trimming edges to resolve end-to-end spacing violations, demonstrating its precision in layout contexts.

For debugging, Calibre Vision AI addresses full-chip integration challenges, such as handling billions of violations with sluggish navigation and limited perspectives. It enables “shift left” strategies, identifying issues early for Calibre-clean resolutions. Features include intelligent debug via check grouping (e.g., bad via arrays or fill overlaps), full-chip analysis at 20x speed (reducing 71GB databases to 1.4GB with instant loading), and cross-team collaboration through bookmarks, ASCII RDB exports, and HTML reports. Integration with the Siemens EDA AI System adds natural language capabilities for tool operations, data reasoning, and knowledge access.

AMD’s testimonial underscores real-world impact: on a design with 600 million errors across 3400 checks, Vision AI grouped them into 381 signals, enabling 2x faster root-cause analysis. Heatmaps revealed systematic issues like fill overlaps with clock cells or missing CM0 in breaker cells, compressing cycle times.

Bottom line: This collaboration between Siemens EDA, TSMC, and AMD exemplifies AI’s transformative role in DRC. By boosting workflows, understanding, fixing, debugging, and collaboration, these tools promise significant productivity gains, potentially shortening design cycles and improving chip reliability. As semiconductor nodes advance, such innovations are essential for maintaining competitive edges in high-stakes industries.

Also Read:

An Assistant to Ease Your Transition to PSS

Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025

Why chip design needs industrial-grade EDA AI

Posted on

Cerebras AI Inference Wins Demo of the Year Award at TSMC North America Technology Symposium

Cerebras AI Inference Wins Demo of the Year Award at TSMC North America Technology Symposium
by Daniel Nenni on 12-07-2025 at 2:00 pm
Categories: Events, Foundries, TSMC

Cerebras TSMC OIP 2025

This is a clear reminder of how important the semiconductor ecosystem is and how closely TSMC works with customers. The TSMC Symposium started 30 years ago and I have been a part of it ever since.  This event is attended by TSMC’s top customers and partners and is the #1 semiconductor networking event of the year, absolutely.

Cerebras Systems, the pioneer in wafer-scale AI acceleration, today announced that its live demonstration of the CS-3 AI inference system received the prestigious Demo of the Year award at the 2025 TSMC North America Technology Symposium in Santa Clara.

The winning demonstration showcased the Cerebras CS-3, powered by the industry’s largest chip, the 4-trillion-transistor Wafer-Scale Engine 3 (WSE-3), delivering real-time, multi-modal inference on Meta’s Llama 3.1 405B model at over 1,800 tokens per second for a single user, and sustaining over 1,000 tokens per second even under heavy concurrent multi-user workloads. Running entirely in memory with no external DRAM bottlenecks, the CS-3 processed complex reasoning, vision-language, and long-context tasks with sub-200-millisecond latency performance previously considered impossible at this scale.

TSMC’s selection committee, composed of senior executives and technical fellows, cited three decisive factors:
  1. Unprecedented single-chip performance on frontier models without multi-node scaling
  2. True real-time interactivity on models larger than 400 billion parameters
  3. Seamless integration of TSMC’s most advanced 5 nm technology with Cerebras’ revolutionary wafer-scale architecture

During the live demo, the CS-3 simultaneously served dozens of concurrent users running Llama 3.1 405B with 128k context windows, answering sophisticated multi-turn questions, generating images from text prompts via integration with Flux.1, and performing real-time document analysis—all while maintaining conversational latency indistinguishable from smaller cloud-based models.

“Wafer-scale computing was considered impossible for fifty years, and together with TSMC we proved it could be done,” said Dhiraj Mallick, COO, Cerebras Systems. “Since that initial milestone, we’ve built an entire technology platform to run today’s most important AI workloads more than 20x faster than GPUs, transforming a semiconductor breakthrough into a product breakthrough used around the world.”

“At TSMC, we support all our customers of all sizes—from pioneering startups to established industry leaders—with industry-leading semiconductor manufacturing technologies and capacities, helping turn their transformative idea into realities,” said Lucas Tsai, Vice President of Business Management, TSMC North America. “We are glad to work with industry innovators likes Cerebras to enable their semiconductor success and drive advancements in AI.”

The CS-3’s memory fabric provides 21 petabytes per second of bandwidth and 44 gigabytes of on-chip SRAM—equivalent to the memory of over 3,000 GPUs—enabling entire 405B-parameter models to reside on a single processor. This eliminates the inter-GPU communication overhead that plagues traditional GPU clusters, resulting in dramatically lower latency and up to 20x higher throughput per dollar on large-model inference.

The recognition comes as enterprises increasingly demand cost-effective, low-latency access to frontier-scale models. Independent benchmarks published last month by Artificial Analysis confirmed the CS-3 as the fastest single-accelerator system for Llama 3.1 70B and 405B inference, outperforming NVIDIA H100 and Blackwell GPU clusters on both tokens-per-second and time-to-first-token metrics.

TSMC’s annual symposium attracts thousands of engineers and executives from across the semiconductor ecosystem. The Demo of the Year award has previously gone to groundbreaking advancements in 3 nm and 2 nm process technology; this year marks the first time an AI systems company has claimed the honor.

Cerebras is now shipping CS-3 systems to customers in healthcare, finance, government, and scientific research. The company also announced general availability of Cerebras Inference Cloud, offering developers instant API access to Llama 3.1 405B at speeds up to 1,800 tokens/second—the fastest publicly available inference for models of this scale.

Bottom line: With this award from TSMC, Cerebras solidifies its position as the performance leader in generative AI inference, proving that wafer-scale computing has moved from bold vision to deployed reality.

Also Read:

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

Exploring TSMC’s OIP Ecosystem Benefits

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

Posted on

Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025

Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025
by Daniel Nenni on 12-02-2025 at 10:00 am
Categories: EDA, Events, Siemens EDA, TSMC

Siemens MediaTek TSMC OIP 2025

In the competitive vertical of mobile System-on-Chip development, SRAM plays a pivotal role, occupying nearly 40% of chip area and directly impacting yield and performance. The presentation “Accelerating SRAM Design Cycles With Additive AI Technology,” co-delivered by Mohamed Atoua of Siemens EDA and Deepesh Gujjar of MediaTek at TSMC’s Open Innovation Platform, addresses the verification challenges in advanced nodes like TSMC’s N2P process. As mobile SoCs push for lower minimum operating voltages (Vmin) to enhance power efficiency, device variations intensify, necessitating rigorous statistical yield qualification: 6-sigma for bitcells and 4-4.5 sigma for periphery logic. Traditional brute-force Monte Carlo simulations, while accurate, are computationally intensive and time-consuming, often leading to iterative design cycles that delay production.

The core motivation stems from these iterative workflows. Failures in verification prompt design fixes, PDK revisions, simulator updates, or additional PVT corners, each requiring full re-runs. MediaTek, leveraging Siemens EDA’s Solido tools, sought a more efficient approach. Enter Additive Learning technology, an AI-driven methodology integrated into the Solido Design Environment. This innovation retains and reuses AI models and simulation data from prior jobs, drastically reducing simulations in subsequent iterations without compromising SPICE-level accuracy.

Solido’s suite includes the High-Sigma Verifier and PVTMC Verifier, both enhanced by Additive Learning. HSV enables verifiable high-sigma analysis, achieving 6-sigma yield verification in thousands of simulations—up to 1,000-1,000,000,000x faster than brute force. PVTMC provides full-coverage verification across PVT corners plus Monte Carlo, 2-10x faster than traditional methods, excels at outlier detection. In traditional flows, five iterations might consume 50 hours; with Solido’s iterative workflow, this drops to 5 hours, saving days or weeks in chip schedules.

The Additive Learning Engine automatically detects reuse opportunities, drawing from a lightweight, optimized Reusable AI Datastore. This datastore supports multi-user access, parallel read/write, and small disk footprints, allowing deletion of full DE results while preserving speedup potential. It stores AI models and past data for fast lookups, ensuring seamless integration into workflows like design sizing changes or PDK updates.

MediaTek’s results demonstrate tangible benefits. In Case 1, verifying 5-sigma bitcell write margin on N2P (clock-to-bitcell flip), the base run required 2,500 simulations, yielding a mean of 120.1 ps and 5-sigma of 131.2 ps. Post-design fix (Vt changes in write driver and column mux), Additive Learning completed verification in just 29 simulations, a 67x speedup, with mean 121.8 ps and 5-sigma 132.5 ps. Case 2 involved 4-sigma instance-level verification (clock-to-data out), where the original 300 simulations gave mean 167.4 ps and 4-sigma 173.1 ps. After Vt updates in control/IO blocks, Additive Learning used 15 simulations (20x faster) matching full re-run results (mean 198 ps, 4-sigma 204.6-204.8 ps).

This technology’s broader adoption underscores its production-grade maturity. NVIDIA, for instance, employs Additive Learning in AI-powered standard cell verification, achieving speedups on incremental runs amid rising design complexity beyond 5nm. Siemens EDA highlights up to 100x boosts to existing AI techniques for verification efficiency. As nodes shrink, such tools are essential for maintaining accuracy while compressing cycles, enabling faster time-to-market for high-yield SoCs.

Bottom line: Additive Learning transforms SRAM design from a bottleneck into an agile process: fast, accurate, and automatic. By reusing models across iterations PDK revisions, sizing tweaks, or tool updates, it exemplifies AI’s role in EDA, as evidenced by MediaTek’s 20-67x gains. This collaboration between Siemens EDA and MediaTek not only accelerates mobile innovation but sets a benchmark for AI integration in semiconductor workflows, promising even greater efficiencies in future nodes.

Also Read:

Transforming Functional Verification through Intelligence

Why chip design needs industrial-grade EDA AI

Hierarchically defining bump and pin regions overcomes 3D IC complexity

CDC Verification for Safety-Critical Designs – What You Need to Know

Posted on

TSMC Formally Sues Ex-SVP Over Alleged Transfer of Trade Secrets to Intel

TSMC Formally Sues Ex-SVP Over Alleged Transfer of Trade Secrets to Intel
by Daniel Nenni on 11-28-2025 at 6:00 am
Categories: Foundries, Intel Foundry, TSMC
3 Comments

TSMC vs Wei Jen Lo

The big semiconductor news this week is the legal action TSMC is taking against former Senior Vice President Wei-Jen Lo. This looks to be a serious game of 3D chess between CC Wei and Lip-Bu Tan so it is worth a look. I got this notice in my inbox early Tuesday morning:

Immediately following, there was an interesting discussion on SemiWiki. Since this story is still unfolding I thought it would be worth while to take a closer look and share perspectives.

Wei-Jen Lo immigrated to the US from Taiwan and earned his PhD in Solid State Physics & Surface Chemistry from U.C. Berkeley in 1979.  He joined TSMC in 2004 after 18 years at Intel in positions including Director of Technology Development and as a Factory Manager running a development facility in Santa Clara, CA.

Joining TSMC after Intel was not uncommon back then. Intel and TSMC did not compete directly and that is how Silicon Valley worked. We changed jobs in pursuit of equity so Wei-Jen Lo only working for two different companies in 40 years is quite remarkable. It also goes to the depth of knowledge he had at both companies.

Here is the TSMC hiring announcement from 2004:

Approved the appointment of Dr. Wei-Jen Lo as Vice President of TSMC Operations II. Both Dr. Wei-Jen Lo and Dr. Mark Liu, who is also a Vice President of TSMC Operations II, report directly to Dr. Rick Tsai, President and Chief Operating Officer for TSMC. Dr. Wei-Jen Lo recently joined TSMC from Intel Corporation where he held various positions in technology development and management. Prior to joining Intel, Dr. Lo served in the IT and semiconductor industries, and he also held teaching and research position in the university in the US.

TSMC and many other semiconductor companies have hired former Intel employees. In fact, you will be hard pressed to find a company that did not have Intel experience inside so this is nothing new. In fact, Dr. Mark Liu also worked for Intel prior to joining TSMC and later became CEO and Chairman of the Board.

The problem as I see it is two-fold:

Wei-Jen Lo told TSMC he was retiring which provided a completely different exit than if he had said he would go to work for a competitor. For example, it was reported that Wei-Jen Lo was allowed to take 20 boxes of hand written notes he had complied over the last 20 years while working at TSMC. That would not have happened if it was known that he was going to work for Intel.

The second problem is that Intel did not publicly announce Wei-Jen Lo’s arrival  which is normally done for the executive staff. This supports the argument of deception. Wei-Jen is said to be a Senior VP at Intel reporting directly to Lip-Bu Tan. He will work in Intel’s manufacturing group and its packaging business which directly competes with TSMC.

On Wednesday morning Lip-Bu Tan sent a message to Intel employees defending the hiring:

“Based on everything we know today, we see no merit to the allegations involving Wei-Jen, and he continues to have our full support. Intel has welcomed back Wei-Jen Lo, who previously spent 18 years at Intel working on the development of Intel’s wafer processing technology before joining TSMC, where he continued his work in their wafer processing technology development.”

On Thursday it was reported that Taiwan prosecutors had raided the homes of the former senior TSMC executive and seized computers after the company accused him of leaking trade secrets. This is both a criminal and civil investigation.

This big question is why?

Wei-Jen Lo is 75 years old and has had a remarkable career working for two semiconductor giants that changed the world. His legacy is one semiconductor professionals like myself honor greatly. Wei-Jen has also worked for some of the most decorated people in the semiconductor industry including Andy Grove, Craig Barrett, Morris Chang, and CC Wei.

Additionally, Wei-Jin Lo owns significant TSMC stock. I found a source that said as of February 28, 2025, Lo held 1,282,328 shares, valued at about US$63 million. Could that be true? And now he risks losing it as a result of a lawsuit? Not to mention the shame of betraying Taiwan’s most valued company? Seriously, why would he do this?

Bottom Line: Hopefully this story has a happy ending. TSMC is still an important supplier to Intel and this will be yet another test of leadership for Lip-Bu Tan. Lip-Bu needs to get in front of this situation before it does irreparable harm to Intel, absolutely.

Also Read:

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

Exploring TSMC’s OIP Ecosystem Benefits

TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging

Posted on

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival
by Daniel Nenni on 11-07-2025 at 6:00 am
Categories: AI, Automotive, Foundries, TSMC

TSMC Kumamoto Fab 2

In the lush landscapes of Kumamoto Prefecture, on Japan’s Kyushu Island, TSMC is etching a new chapter in global chip production. The TSMC Kumamoto facility, operationalized through its wholly-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM), represents the Taiwanese giant’s bold foray into Japan, the first dedicated wafer fab outside Taiwan, the U.S., and Europe.

Announced in 2021, this project embodies a strategic pivot toward diversified, resilient manufacturing. With an initial investment exceeding $8.6 billion, Kumamoto underscores TSMC’s commitment to serving key Asian clients while bolstering Japan’s domestic semiconductor ecosystem.

The journey began with groundbreaking in 2022, transforming a sprawling industrial site in Kikuyo Town into a state-of-the-art cleanroom. Construction progressed swiftly, with Taiwanese engineers relocating en masse to oversee integration. By late 2024, JASM’s first fab commenced mass production, focusing on mature yet vital process nodes: 22/28nm and 12/16nm. These nodes are ideal for automotive semiconductors, image sensors, and microcontrollers, sectors where Japanese powerhouses like Sony and Denso dominate.

The facility’s monthly capacity targets 55,000 wafers, powered entirely by renewable energy sources, aligning with Japan’s green manufacturing mandates. As of April 2025, JASM’s workforce has swelled to around 2,400, including 527 new local hires, fostering a blend of Taiwanese expertise and Japanese precision. This infusion has not only created jobs but also sparked a skills renaissance in Kyushu, a region long synonymous with electronics but starved of cutting-edge fabs. This fab was dubbed the “Knight Castle” by locals since construction was done 24 hours a day.

Kumamoto’s strategic imperative is twofold: Geopolitically, it mitigates risks from Taiwan’s exposure to cross-strait tensions, diversifying TSMC’s footprint amid U.S.-China frictions. Economically, it taps into Japan’s resurgence under the “Semiconductor Revival Plan,” backed by subsidies from the Ministry of Economy, Trade and Industry.

This funding is part of a national initiative which aims to reclaim 10% of global chip production by 2030. For TSMC, Kumamoto secures proximity to loyal customers: Sony’s image sensors for smartphones and cameras, Denso’s automotive chips for electric vehicles, and emerging AI peripherals. In an era where automotive semis face slumps, exacerbated by delayed EV adoption, the fab’s specialization offers stability. Industry watchers project profitability by late 2025, with yields already performing robustly.

Yet, expansion hasn’t been seamless. The second fab, earmarked for advanced 6/7nm processes on a 321,000-square-meter plot adjacent to the first, has encountered headwinds. Initially slated for Q1 2025 groundbreaking, construction was deferred to mid-year due to severe traffic congestion from the initial site’s operations (commutes ballooning from 15 minutes to an hour) irking residents. TSMC Chairman C.C. Wei cited these local pains during the June 2025 shareholders’ meeting, emphasizing dialogues with Japanese authorities for infrastructure upgrades. Further delays in 2025 stemmed from softer automotive demand and a pivot toward U.S. investments, pushing mass production to late 2027. TSMC builds fabs closely tied to customer demand so this a good example of intelligent semiconductor business decisions.

Despite these challenges, TSMC reaffirmed its commitment in August 2025 with board member Paul Liu quashing rumors of diminished Japanese focus. The second fab promises elevated capabilities, including 40nm variants for industrial applications, potentially doubling output and attracting more clients.

Beyond wafers, Kumamoto catalyzes regional transformation. Kyushu’s IC production value hit ¥1 trillion in 2024 for the first time in 16 years, fueled by TSMC’s ripple effects. Local suppliers, from equipment makers to materials firms, now furnish 60% of needs, nurturing a self-sustaining cluster. Governor Takashi Kimura has championed community buy-in, securing promises for green spaces and training programs amid wastewater monitoring starting January 2025.

Bottom live: Kumamoto could spawn a third fab post-2030, embedding TSMC deeper in the “semiconductor triangle” of Taiwan, Japan, and the U.S. As AI and EVs propel chip demand, this outpost fortifies supply chains, blending Eastern innovation with Western resilience. In Kumamoto, silicon flows not just as commerce, but as a bridge across borders proving that in the chip wars, collaboration outpaces isolation. For TSMC, it’s a testament to enduring partnerships, for Japan it is a revival etched in silicon, absolutely.

Also Read:

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

Exploring TSMC’s OIP Ecosystem Benefits

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging

Posted on

Memory Matters: The State of Embedded NVM (eNVM) 2025

Memory Matters: The State of Embedded NVM (eNVM) 2025
by Daniel Nenni on 11-06-2025 at 6:00 am
Categories: GlobalFoundries, IP, Samsung Foundry, TSMC
1 Comment

NVM Survey 25 Square Banner for SemiWiki 400x400 px

Make a difference and take this short survey. It asks about your experience with embedded non-volatile memory technologies. The survey is anonymous, and the results will be shared in aggregate to help the industry better understand trends: 2025 Embedded Non-Volatile Memory Survey.

We are now in the AI era where data is the lifeblood of innovation, and embedded NVM stands as a cornerstone technology, retaining information without using power and enabling everything from MCUs and IoT SoCs to automotive controllers and secure elements.

As of November 2025, embedded NVM is moving fast. Edge data is surging, AI features are landing on MCUs and SoCs, and power budgets are tighter than ever. Memory is central to the devices we build. This survey looks at where eNVM stands today in terms of markets, technology, and adoption, and where it’s heading next.

Market Overview and Growth

Embedded emerging NVM, including MRAM, RRAM/ReRAM, and PCM, is entering a broader adoption phase across MCUs, connectivity, and edge-AI devices, with momentum building in automotive and industrial markets. Research firm Yole Group indicate the embedded emerging segment should exceed $3B by 2030, reflecting wider availability in mainstream process nodes and stronger pull where eFlash is no longer a good fit at ≤28 nm.

Technological Advancements

Embedded flash remains foundational, but scaling limits at advanced nodes have pushed MRAM, ReRAM, and embedded PCM to the foreground. Foundries and IDMs are extending embedded options beyond 28/22 nm planar CMOS toward 10–12 nm-class platforms, including FinFET. Yole highlights aggressive foundry roadmaps: TSMC has established high-volume MRAM/ReRAM and is preparing 12nm FinFET ReRAM/MRAM for 2025 and beyond. Samsung, GlobalFoundries, UMC, and SMIC are accelerating embedded MRAM/ReRAM/PCM across general-purpose MCUs and high-performance automotive designs. STMicroelectronics stands out as the IDM fully committed to embedded PCM, ramping xMemory solutions for industrial and automotive MCUs, with 18nm FD-SOI extending reach after 2025.

In parallel, BCD and HV-CMOS flows are incorporating embedded NVM as practical replacements for EEPROM/OTP in analog, power management, and mixed-signal designs. On the IP side, suppliers are qualifying embedded NVM technologies for these platforms, giving designers more options where cost, endurance, and retention outweigh legacy choices. Beyond code and data storage, in-/near-memory compute concepts using eNVM are gaining interest for low-power edge AI inference.

Drivers, Challenges, and Use Cases

Automotive remains the center of gravity for embedded emerging NVM, and 2025 brings a noticeable uptick in secure ICs and industrial MCUs as more products reach production. In practice, ReRAM, MRAM, and PCM each have a role: ReRAM is gaining traction in several high-volume categories; MRAM and PCM are attractive where speed and endurance dominate. The mix varies by node, application, and vendor roadmap.

The challenges are familiar: integrating eNVM at advanced logic nodes, trading off endurance and retention, qualifying to automotive-grade reliability, and achieving cost-effective density as embedded code and AI parameters grow. The trend line is positive, with PDK/IP availability growing and capacity ramping, so these issues are being addressed rather than deferred.

Outlook

By 2030, embedded NVM will underpin more on-chip AI features and practical in-/near-memory compute blocks, with broader use in neuromorphic-inspired accelerators at the edge. Yole’s projections indicate that the embedded emerging segment is now the primary engine of growth, led by ReRAM in high-volume MCUs and analog ICs, while MRAM and embedded PCM consolidate in performance-critical niches. As edge data grows, eNVM’s role expands from “just storage” to part of the computing fabric, redefining efficiency and making embedded memory more central than ever to device intelligence.

Bottom line: In 2025, embedded NVM isn’t just memory, it’s the enabler of intelligent, persistent systems on chip. With accelerating adoption across MCUs and edge SoCs, and clear roadmaps from leading foundries and IDMs, the trajectory is set: embedded memory matters more than ever. Let us know your opinion by taking the short survey.

Take the 2025 Embedded Non-Volatile Memory Survey Here.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston

Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA

Posted on

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design

AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor Design
by Daniel Nenni on 10-28-2025 at 10:00 am
Categories: EDA, Events, Foundries, Siemens EDA, TSMC

AI Driven DRC Productivity Optimization Siemens AMD TSMC

The semiconductor industry is undergoing a transformative shift with the integration of AI into DRC workflows, as showcased in the Siemens EDA presentation at the 2025 TSMC OIP. Titled “AI-Driven DRC Productivity Optimization,” this initiative, led by Siemens EDA’s David Abercrombie alongside AMD’s Stafford Yu and GuoQin Low, highlights a collaborative effort to enhance productivity and efficiency in chip design. The presentation outlines a comprehensive AI system that revolutionizes the entire EDA workflow, from knowledge sharing to automated fixing and debugging.

At the core of this innovation is the Siemens EDA AI System, which leverages a GenAI interface, knowledge base, and data lake to integrate AI tools across the portfolio. This system, deployable on customer hardware or cloud environments, supports a unified installation process and offers flexibility to incorporate customer data and models. Tools like the AI Docs Assistant and Calibre RVE Check Assist boost user understanding by providing instant answers and leveraging TSMC design rule data, respectively. The AI Docs Assistant, accessible via browser or integrated GUIs, uses retrieval-augmented generation to deliver relevant citations, while Calibre RVE Check Assist enhances debugging with specialized images and descriptions from TSMC.

Collaboration is a key pillar, with features like Calibre RVE Check Assist User Notes enabling in-house knowledge sharing. Designers can capture fixing suggestions and images, creating a shared knowledge base that enhances DRC-fixing flows across organizations. Meanwhile, Calibre DesignEnhancer automates the resolution of DRC violations on post-routed designs, using analysis-based modifications to insert sign-off DRC-clean interconnects and vias. This tool’s ability to handle complex rules and dependencies makes it a standalone DRC fixing solution.

Calibre Vision AI addresses the unique challenges of full-chip integration by offering AI-guided DRC analysis. It provides lightning-fast navigation through billions of errors, intelligent debug clustering, and cross-user collaboration tools like bookmarks and HTML reports. AMD’s testimonial underscores a 2X productivity boost in systematic error debugging, with Vision AI reducing OASIS database sizes and load times significantly. Signals analysis, such as identifying fill overlaps with clock cells or CM0 issues in breaker cells, accelerates root-cause identification.

This AI-driven approach, bolstered by AMD and TSMC collaborations, optimizes DRC sign-off productivity by boosting workflows, understanding, fixing, debugging, and collaboration. As the industry moves toward more complex designs, Siemens EDA’s AI system sets a new standard, promising faster cycle times and enhanced design robustness, paving the way for future innovations in semiconductor technology.

For more information contact Siemens EDA

Great presentation, absolutely.

Also Read:

Visualizing hidden parasitic effects in advanced IC design 

Protect against ESD by ensuring latch-up guard rings

Something New in Analog Test Automation

Posted on

Exploring TSMC’s OIP Ecosystem Benefits

Exploring TSMC’s OIP Ecosystem Benefits
by Daniel Nenni on 10-10-2025 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, Events, Foundries, IP, TSMC

TSMC Booth

Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC with EDA providers, IP developers, cloud partners, design centers, and value chain players. This network, now spanning over 100 partners, has invested trillions of dollars cumulatively to align around TSMC’s technology roadmap, enabling faster innovation and specialization. As of 2025, OIP continues to evolve with recent expansions like the 3DFabric Alliance accelerating 3D IC advancements for AI and HPC.

The ecosystem’s core strength lies in its comprehensive alliances: EDA Alliance for certified tools, IP Alliance for silicon-verified blocks, Cloud Alliance for scalable design environments, Design Center Alliance (DCA) for expert services, Value Chain Alliance (VCA) for backend support, and specialized groups like 3DFabric for advanced packaging. These components lower barriers, ensuring “first-time silicon success” and driving shared value. Below, we break down the primary benefits for customers (chip designers), partners, and the broader industry.

1. Accelerated Design and Time-to-Market

OIP drastically shortens the path from concept to production, addressing the semiconductor industry’s relentless pace. By integrating TSMC’s process technologies with partner tools and IP, it reduces design cycle times by providing pre-validated interfaces and flows.

For instance:
  • Cloud-Based Design: Through the Cloud Alliance (partners like AWS, Google Cloud, and Microsoft Azure), customers overcome in-house compute limits, enabling “design-in-the-cloud” for scalability and agility. This has cut time-to-market for complex chips by weeks to months.
  • AI-Assisted Flows: At the 2024-2025 OIP Forums, ecosystem demos showcased AI-optimized 2D/3D IC designs, boosting productivity for AI and 5G applications.
  • 3D Innovation: The 3DFabric Alliance, launched in 2022, speeds silicon stacking and chiplet integration, as seen in AMD’s TSMC-SoIC-based CPUs, which achieved energy-efficient HPC breakthroughs.

Statistics highlight the impact: OIP has enabled over 1,800 chip tape-outs, with partners like Silicon Creations contributing to 1,000+ advanced-node designs. Testimonials from Synopsys emphasize how OIP’s multi-die tools deliver “powerful and efficient processing” for hyperscale computing.

2. Cost Reduction and Efficiency Gains

OIP minimizes financial risks by democratizing access to premium resources, allowing smaller firms to compete with giants.

  • Lower Barriers: Silicon-verified IP catalogs (the industry’s largest) and EDA certifications reduce R&D duplication, cutting development costs by up to 30-50% through reusable blocks like PLLs and SerDes.
  • Shared Investments: Ecosystem collaborations, backed by billions in annual spending, spread costs across partners. For example, Siemens EDA Calibre 3DThermal integration with TSMC processes provides thermal analysis without custom tooling.
  • Design Services: DCA and VCA offer outsourced expertise for testing and packaging, ideal for resource-constrained teams.

This efficiency has been pivotal for mobile and IoT innovations, where rapid prototyping via OIP’s Virtual Design Environment (launched 2018) avoids expensive iterations.

3. Enhanced Collaboration and Ecosystem Synergy

OIP’s “partner management portal” via TSMC-Online fosters seamless communication, turning competition into co-creation.

  • Supply Chain Alignment: Standardized interfaces (e.g., 3Dblox for chiplet packaging) ensure interoperability, as noted by Siemens EDA: “OIP has been pivotal to advancing certified flows.”
  • Global Forums: Annual events like the 2025 North America OIP Forum in Santa Clara unite 1,000+ attendees for multi-track sessions on AI, photonics, and RF, sparking real-time problem-solving.
  • Award-Winning Partnerships: 2025 honorees like Teradyne (for 3DFabric testing) and Silicon Creations (ninth straight Mixed-Signal IP award) exemplify how OIP drives mutual growth, with TSMC’s Aveek Sarkar praising their role in “energy-efficient AI chip innovation.”
4. Industry-Wide Innovation and Scalability

Beyond individual gains, OIP propels the sector forward by supporting emerging tech like 2nm nodes, UCIe standards, and silicon photonics. It has nurtured innovations in automotive, 5G, and edge AI, with partners like imec contributing R&D for low-volume prototyping. The result? A resilient ecosystem that shortens “time-to-revenue” while promoting sustainability through efficient designs.

Bottom line: TSMC’s OIP transforms semiconductor development from siloed efforts to a vibrant, collaborative powerhouse. As AI demands surge, its benefits of speed, savings, synergy, and scalability position it as indispensable, empowering innovators to outpace Moore’s Law. For deeper dives, explore TSMC’s OIP page and the most recent forum recap: TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging.

Also Read:

Analog Bits Steps into the Spotlight at TSMC OIP

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Posted on

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®
by Daniel Nenni on 10-08-2025 at 8:00 am
Categories: Foundries, TSMC

ETC 2025 TSMC

In a landmark presentation at the 2025 IEEE Electronic Components and Technology Conference (ECTC), TSMC unveiled a groundbreaking advancement in thermal management: Direct-to-Silicon Liquid Cooling integrated directly onto its CoWoS® platform. This innovation, detailed in the paper “Direct-to-Silicon Liquid Cooling Integrated on CoWoS® Platform,” addresses the escalating thermal challenges posed by HPC and AI applications, where power densities are surging beyond traditional cooling limits. As AI accelerators and data center chips push thermal design power toward kilowatt levels, TSMC’s solution promises to shatter the “thermal wall,” enabling denser, faster, and more efficient semiconductor designs.

The “thermal wall” refers to the fundamental barrier where heat generation outpaces dissipation capabilities, throttling performance and reliability in advanced nodes. With the rise of 2.5D/3D packaging technologies, chips now integrate multiple dies, high-bandwidth memory (HBM) stacks, and interposers on a single package, amplifying power densities to over 4.8 W/mm². Air cooling, once sufficient for consumer-grade processors, falls short for HPC workloads. Even advanced air-cooled heatsinks struggle with TDPs exceeding 1 kW, leading to hotspots that degrade silicon integrity and limit clock speeds. Liquid cooling has emerged as a necessity, but conventional methods—relying on bulky external loops or thermal interface materials (TIMs)—introduce inefficiencies, adding thermal resistance and manufacturing complexity.

TSMC’s Direct-to-Silicon Liquid Cooling redefines this paradigm by embedding microfluidic channels directly into the silicon structure, bypassing TIMs for near-zero thermal impedance. At the heart of this technology is the Si-Integrated Micro Cooler, a silicon-based solution fusion-bonded to the chip’s backside. Demonstrated on a 3.3X-reticle CoWoS®-R package—a massive ~3,300 mm² interposer supporting multiple logic dies and HBM stacks—the system achieves junction-to-ambient thermal resistance (θJA) as low as 0.055 °C/W at a coolant flow rate of 40 ml/s. This outperforms lidded liquid cooling with TIMs (0.064 °C/W) by nearly 15%, enabling sustained operation at over 2.6 kW TDP with a temperature delta under 63°C.

CoWoS®  is TSMC’s flagship 2.5D packaging technology, pivotal for AI giants like NVIDIA’s GPUs and AMD’s Instinct accelerators. It stacks chips on a silicon interposer for ultra-high interconnect density, supporting up to 12 HBM4 stacks in future “Super Carrier” iterations spanning 9 reticles. However, as interposers scale to 2,500 mm² or larger, heat flux intensifies, risking electromigration and yield loss. The IMC-Si integrates seamlessly into CoWoS®-R and upcoming CoWoS®-L variants, which incorporate backside power delivery networks (BSPDN) and embedded deep trench capacitors (eDTCs) for enhanced power stability. Microchannel designs—featuring square pillars, trenches, or flat planes—optimize fluid dynamics, with pillar structures proving superior for turbulent flow and heat extraction.

The demonstration highlights practical viability. TSMC tested prototypes with deionized water as coolant, achieving power densities exceeding 7 W/mm² on logic chip backsides. Fusion bonding ensures hermetic seals, preventing leaks in high-pressure environments, while low-temperature processes maintain compatibility with 1.6nm-class nodes. Early results show no degradation in electrical performance, with signal integrity preserved across hybrid bonding interfaces.

This breakthrough extends beyond cooling; it’s a cornerstone of TSMC’s 3DFabric ecosystem, aligning with “More than Moore” strategies like hybrid bonding and CMOS 2.0. By eliminating TIMs, it reduces assembly costs and variability, while enabling trillion-transistor monolithic-like systems. For data centers, it slashes rack-level power—potentially halving cooling infrastructure needs—and supports immersion-compatible designs. In edge AI and 5G, compact IMC-Si modules could fit mobile HPC, boosting efficiency in autonomous vehicles and AR/VR.

Challenges remain: scaling microfluidic fabrication to high volumes, ensuring coolant purity to avoid corrosion, and integrating with emerging materials like silicon carbide interposers for even higher thermal conductivity. Yet, TSMC’s track record—powering 80% of advanced AI chips—positions it to lead commercialization by 2027.

Dr. Kevin Zhang, TSMC’s Deputy Co-COO and Senior Vice President, emphasized: “Direct-to-Silicon Liquid Cooling breaks the thermal wall, unlocking the full potential of CoWoS® for exascale AI. This isn’t just incremental; it’s transformative for sustainable computing.”

As AI workloads explode, TSMC’s innovation heralds a cooler, greener future for semiconductors, where heat is no longer the limiter but a solved equation.

Also Read:

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Posted on

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award
by Daniel Nenni on 10-06-2025 at 10:00 am
Categories: Chiplet, Events, Foundries, TSMC

TSMC 3D Fabric Packaging TSMC OIP 2025

In a significant milestone for the semiconductor industry, Teradyne was honored as the 2025 TSMC Open Innovation Platform® Partner of the Year for TSMC 3DFabric® Testing. This award, announced on September 25, 2025, underscores the deep collaboration between Teradyne, a leader in automated test equipment and robotics, and TSMC, the world’s premier semiconductor foundry. The recognition highlights their joint efforts in advancing multi-die test methodologies for chiplets and TSMC’s CoWoS® advanced packaging technology, marking a pivotal step in the shift toward chiplet-based architectures essential for AI and high-performance computing.

Teradyne, headquartered in North Reading, Massachusetts, specializes in designing and manufacturing automated test solutions for semiconductors, electronics, and robotics systems. Its portfolio ensures high-quality performance across complex devices, from wafer-level testing to final assembly. TSMC dominates the foundry market with cutting-edge process nodes and packaging innovations. The partnership traces back to at least 1999, when TSMC adopted Teradyne’s automatic test equipment for 0.18-micron test chips. Over the years, this alliance has evolved, with Teradyne contributing to TSMC’s ecosystem through innovations in test strategies for heterogeneous integration.

At the heart of this award is TSMC’s OIP, launched in 2008 to foster collaboration among design partners, IP providers, and ecosystem members. OIP accelerates innovation by integrating process technology, EDA tools, and IP, enabling faster implementation of advanced designs. Celebrating its 15th anniversary in 2023, OIP has grown from 65nm nodes onward, addressing rising design complexities. Within this framework, the 3DFabric Alliance, introduced in 2023, focuses on overcoming challenges in 3D integration and advanced packaging.

TSMC 3DFabric® represents a comprehensive suite of 3D silicon stacking and advanced packaging technologies, encompassing both 2.5D and 3D architectures like CoWoS and InFO. These enable heterogeneous integration, boosting system-level performance, power efficiency, and form factors for applications in AI accelerators, 5G, and HPC. CoWoS, in particular, supports multi-die packages by stacking chips on silicon interposers, ideal for demanding AI workloads.

Through the 3DFabric Alliance, Teradyne and TSMC have pioneered test methodologies that enhance silicon bring-up efficiency and test quality. Teradyne’s investments in UCIe, GPIO, and streaming scan test solutions facilitate scalable, high-quality testing of die-to-die interfaces. UCIe, an open standard for chiplet interconnects, ensures seamless data transfer between dies, while streaming scan enables high-speed testing over these interfaces at wafer sort or probing stages. This reduces defect escapes, lowers quality costs, and accelerates time-to-market for 3D ICs used in AI and cloud datacenters.

Shannon Poulin, President of Teradyne’s Semiconductor Test Group, emphasized the value of TSMC’s collaborative ecosystem: “At Teradyne, we strongly believe in the open and collaborative ecosystem approach of TSMC’s Open Innovation Platform and look forward to continuing our partnership to drive innovation and deliver exceptional value to our customers.” Aveek Sarkar, Director of TSMC’s Ecosystem and Alliance Management Division, congratulated Teradyne, noting their contributions to improving silicon bring-up and enabling AI proliferation through energy-efficient compute.

The award was unveiled at the 2025 TSMC North America OIP Ecosystem Forum in Santa Clara, California, on September 24, 2025. This event gathered industry leaders to explore AI’s role in next-generation designs for TSMC’s advanced nodes like A16, N2, and N3. Highlights included discussions on AI-accelerated chip design, multi-die systems, and 3DFabric advancements, with partners showcasing tools for HPC and energy efficiency.

This partnership not only strengthens Teradyne’s position in AI hardware testing but also propels the industry toward more efficient, scalable semiconductor solutions. As demand for AI and cloud infrastructure surges, collaborations like this will be crucial in shortening development cycles and enhancing reliability. Looking ahead, Teradyne and TSMC’s ongoing innovations promise to redefine heterogeneous integration, driving the next wave of technological breakthroughs

Also Read:

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Analog Bits Steps into the Spotlight at TSMC OIP